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STM32F383RC Datasheet(PDF) 25 Page - STMicroelectronics |
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STM32F383RC Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 125 page  DocID023367 Rev 2 25/125 STM32F383xx Functional overview 47 master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces can operate in half-duplex mode only. Refer to Table 9 for the features between SPI1, SPI2 and SPI3. 3.22 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The device embeds a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception. 3.23 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. 3.24 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Table 9. STM32F383xx SPI/I2S implementation SPI features(1) 1. X = supported. SPI1 SPI2 SPI3 Hardware CRC calculation X X X Rx/Tx FIFO X X X NSS pulse mode X X X I2S mode XXX TI mode XXX I2S full-duplex mode |
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