AS4C4M16S datasheet(7/53 Pages) ALSC

7 / 53 page

FEBRUARY 2011

AS4C4M16S

Commands

BankActivate

(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address)

The Bank Activate command activates the idle bank designated by the BA0, 1 signal. By latching the

row address on A0 to A11 at the time of this command, the selected row access is initiated. The read or

write operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank

activation. A subsequent BankActivate command to a different row in the same bank can only be issued

after the previous active row has been precharged (refer to the following figure). The minimum time

interval between successive Bank Activate commands to the same bank is defined by tRC(min.). The

SDRAM has four internal banks on the same chip and shares part of the internal circuitry to reduce chip

area; therefore it restri cts the back-to-back activation of the two banks. tRRD(min.) specifies the minimum

time required between activating different banks. After this command is used, the Write command and

the Block Write command perform the no mask write operation.

CLK

Tn+3

Tn+4

Tn+5

Tn+6

ADDRESS

Bank A

Row Addr.

Bank A

Col Addr.

Bank B

Row Addr.

Bank A

Row Addr.

RAS# - CAS# delay(tRCD)

RAS# - RAS# delay time(tRRD)

COMMAND

Bank A

Activate

NOP

R/W A with

AutoPrecharge

Bank B

Activate

NOP

Bank A

Activate

RAS# - Cycle time(tRC)

AutoPrecharge

Begin

Don’t Care

Figure 3. BankActivate Command Cycle (Burst Length = n)

Bank Precharge command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)

The BankPrecharge command precharges the bank designated by BA signal. The precharged bank

is switched from the active state to the idle state. This command can be asserted anytime after t RAS(min.)

is satisfied from the BankActivate command in the desired bank. The maximum time any bank can be

active is specified by tRAS(max.). Therefore, the precharge function must be performed in any active bank

within tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be

activated again.

Precharge All command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = D

on’t care, A10 = "H", A0-A9 and A11 = Don't care)

The PrechargeAll command precharges all banks simultaneously and can be issued even if all

banks are not in the active state. All banks are then switched to the idle state.

Read command

(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A7 = Column Address)

The Read command is used to read a burst of data on consecutive clock cycles from an active row

in an active bank. The bank must be active for at least t

RCD

(min.) before the Read command is issued.

During read bursts, the valid data-out element from the starting column address will be available following

the CAS# latency after the issue of the Read co mmand. Each subsequent data-out element will be valid

by the next positive clock edge (refer to the followi ng figure). The DQs go into high-impedance at the end

of the burst unless other command is initiated. The burst length, bur st sequence, and CAS# latency are

determined by the mode register, which is already programmed. A full-page burst will continue until

terminated (at the end of the page it will wrap to column 0 and continue.

Rev2.0 May 2014

AS4C4M16S Datasheet(PDF) 7 Page - Alliance Semiconductor Corporation

AS4C4M16S Datasheet(HTML) 7 Page - Alliance Semiconductor Corporation

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