APDS-9009 datasheet(7/22 Pages) BOARDCOM

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APDS-9200

Data Sheet

I2C Protocol

Interface and control of the APDS-9200 is accomplished

through an I2C serial compatible interface (standard or fast

mode) to a set of registers that provide access to device control

functions and output data. The device supports a single slave

address of 0x52 hex using 7 bit addressing protocol. (Contact

the factory for other addressing options.)

I2C Register Read

The registers can be read individually or in block read mode.

When two or more bytes are read in block read mode, reserved

referenced. If the last valid address has been reached, but the

master continues with the block read, the address counter in

the device will not roll over and the device returns 00HEX for

every subsequent byte read.

The block read operation is the only way to ensure correct data

read out of multi-byte registers and to avoid splitting of results

with HIGH and LOW bytes originating from different

conversions. During block read access on LS result registers, the

result update is blocked.

If a read access is started on an address belonging to a

non-readable register, the APDS-9200 will re-turn NACK until

the I2C operation is ended.

Read operations must follow the timing diagram in Figure 16.

I2C Register Write

The APDS-9200 registers can be written to individually or in

block write mode. When two or more bytes are written in block

write mode, reserved registers and read-only registers are

skipped. The transmitted data is automatically applied to the

next writable register. If a register includes read (R) and

read/write (RW) bits, the register is not skipped. Data written to

read-only bits are ignored.

If the last valid address of the APDS-9200 address range is

reached but the master attempts to continue the block write

operation, the address counter of the APDS-9200 will not roll

over. The device will return NACK for every following byte sent

by the master until the I2C™ operation is ended.

If a write access is started on an address belonging to a

non-writeable register, the APDS-9200 will return NACK until

the I2C™ operation is ended.

Write operations must follow the timing diagram in Figure 17.

Figure 16 I2C Register Read

Figure 17 I2C Register Write

Slave Addr

7 Bit

Address

8 Bit

Slave Addr

7 Bit

Data

8 Bit

Slave Addr

7 Bit

Address

8 Bit

Slave Addr

7 Bit

Data

8-Bit

Data

8-Bit

A…

Data

8-Bit

From Master to Slave

From Slave to Master

Start Condi on

Stop Condi on

Acknowledge (ACK)

Not Acknowledge (NACK)

Read

Write

Read

Write

Slave Addr

7 Bit

Address

Data

8-Bit

Slave Addr

7 Bit

Address

Data

8-Bit

Data

8-Bit

A…

Data

8-Bit

Write

From Master to Slave

From Slave to Master

Start Condi on

Stop Condi on

Acknowledge (ACK)

Not Acknowledge (NACK)

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