PC87334VLJ datasheet(27/102 Pages) NSC

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20 Configuration Registers (Continued)

Bit 1

DRV2 DR23 select

0 Pin 49 (PQFP) or pin 47 (TQFP) is DRV2

1 Pin 49 (PQFP) or pin 47 (TQFP) is DR23

DR23 is asserted when either drive 2 or drive 3 is ac-

cessed (except during logical drive exchangesee bit

3 of TDR)

The value of DR23 is undefined when working in four

drive encoded mode (bit 4 of FER is 1) The PC87334

assumes DRV2 is 1 when bit 1 of ASC is 1

Bit 2

Enhanced TDR support

0 TDR read is a function of bit 0 of the FCR configura-

tion register

Pin 59 (PQFP) or pin 57 (TQFP) is IOCS16

Pin 56 (PQFP) or pin 54 (TQFP) is IDEHI VLD0

1 Pin 59 (PQFP) or pin 57 (TQFP) is DRID0 input The

PC87334 assumes IOCS16 is active when bit 2 of

ASC is 1

Pin 56 (PQFP) or pin 54 (TQFP) is DRID1VLD0

input

Bit 2 of ASC should be set to one before the FDD is

accessed

thus preventing contention between

IDEHI and DRID1

The PC87344 provides full TDR support

Bit 3

PNF status bit This bit reflects the value of the PNF

pin It is a read only bit data written to this bit is ig-

nored It is undefined when the pin is configured as

DRV2 or DR23 This bit is 1 when the FDC is powered

down

0 Indicates floppy drive is connected

1 Indicates printer is connected

Bit 4

Reserved

Bit 5

The value of this bit is reflected on bit 3 of CNFGA

ECP register

Bits 6 7

System Operation Mode The PC87334 can be

configured to either PC-AT PS2 or Model 30

modes

00 Model 30 mode

01 PS2 mode

10 Reserved and illegal

11 PC-AT mode

2510 Infrared Configuration Register

(IRC Index e 0Eh)

On reset this register is initialized to zero Some bits are

reserved for future use The value of the reserved bits may

not be altered by software a read modify write operation is

required to modify this register

Bit 0

UART2 Interface Mode This bit is used for run-

time selection of either Normal (Modem) UART or

Serial Infra Red (SIR)

0 Normal (MODEM) mode

1 SIR mode

Bit 1

SIR HalfFull Duplex configuration bit

0 Full Duplex Both transmitter and receiver are

enabled simultaneously

1 Half Duplex The receiver input is blocked (in-

ternally forced low) when the transmitter is on

(when UART2’s SOUT2 is ‘0’)

In Normal (MODEM) mode this bit is ignored

Bits 3 2

SIR pins allocation These bits are used to con-

figure the PC87334 according to the SIR signals

connection in the assembled board

00 SIR disabled and UART2 in Normal (MO-

DEM) mode Bits 4 2 1 and 0 of IRC are

ignored

01 SIR signals on UART2 pins IRTX on pin 63

(PQFP) or pin 61 (TQFP) and IRRX on pin

68 (PQFP) or pin 66 (TQFP)

10 Reserved

11 SIR signals on IDE pins (option

2) IRTX

on pin 56 (PQFP) or pin 54 (TQFP) and

IRRX on pin 59 (PQFP) or pin 57 (TQFP)

IDE DMA should not be configured or used

For UART2 pin functionssee the pin de-

scriptions in Section 10

Bit 4

SIR transmitter drive control bit

0 When IRTX is active it is active for 16 ms

1 When IRTX is active it is active for 316

baud

In Normal (MODEM) mode this bit is ignored

Bits 7 6 5

Reserved for future use (implemented as read

write bits) The value of the reserved bits may

not be altered by software a read modify write

operation is required to modify this register

26 POWER-DOWN OPTIONS

The PC87334 places special emphasis on power manage-

ment Power management methods can be divided into two

major groups

Group 1

Full device power-downthe entire PC87334

SuperIO is powered-down and thus disabled

Group 2

Specific function power-downspecific SuperIO

modules (FDC UART1 UART2 IDE ECP or Par-

allel Port) are powered-down and thus disabled

All power-down modes are enhanced by a new feature

which allows the output pins associated with a specific func-

tion (FDC UART1 UART2 IDE Parallel Port) to be TRI-

STATE pins and reduces current leakage by blocking their

inputs

Four modules in the PC87334 are operated by the internal

clockFDC UART1 UART2 and ECP These modules can

be powered-down or disabled by stopping their associated

internal clocks

In addition

all four modules can be

powered-down or disabled by stopping the external crystal

oscillator

Modules which do not use a clock the IDE and Parallel Port

(SPPEPP) can be powered-down or disabled by simply

blocking access to them

All the above power-down modes can be achieved using

the power-down methods from Group 1 or Group 2 as de-

scribed in the following sections

PC87334VLJ Datasheet(PDF) 27 Page - National Semiconductor (TI)

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