PC87334VLJ datasheet(6/102 Pages) NSC

6 / 102 page

List of Tables

TABLE 1-1

Pin Descriptions (Alphabetical)

TABLE1-2

SIR Pin Allocation

TABLE 2-1

Default Configurations Controlled by Hardware

TABLE 2-2

Index and Data Register Optional Locations

TABLE 2-3

Encoded Drive and Motor Pin Information

TABLE 2-4

Primary and Secondary Drive Address Selection

TABLE 2-5

Parallel Port Addresses

TABLE 2-6

COM Port Selection for UART1

TABLE 2-7

COM Port Selection for UART2

TABLE 2-8

Address Selection for COM3 and COM4

TABLE 2-9

Logical Drive Exchange

TABLE 2-10

Parallel Port Mode

TABLE 2-11

Methods to Achieve Group 1 Power-Down Modes

TABLE 3-1

TABLE 3-2

Drive Enable Values

TABLE 3-3

TDR Operation Modes

TABLE 3-4

Media ID Bit Functions

TABLE 3-5

Tape Drive Assignment Values

TABLE 3-6

Write Precompensation Delays

TABLE 3-7

Default Precompensation Delays

TABLE 3-8

Data Rate Select Encoding

TABLE 4-1

Typical Format Gap Length Values

TABLE 4-2

Typical Format GAP3 Length Values Based on PC Compatible Diskette Media

TABLE 4-3

DENSEL Default Encoding

TABLE 4-4

DENSEL Encoding

TABLE 4-5

Head Settle Time Calculation

TABLE 4-6

Effect of Drive Mode and Data Rate on Format and Write Commands

TABLE 4-7

Effect of GAP and WG on Format and Write Commands

TABLE 4-8

Sector Size Selection

TABLE 4-9

SK Effect on the Read Data Command

TABLE 4-10

Result Phase Termination Values with No Error

TABLE 4-11

SK Effect on the Read Deleted Data Command

TABLE 4-12

Maximum Recalibrate Step Pulses Based on R255 and ETR

TABLE 4-13

Scan Command Termination Values

TABLE 4-14

Status Register 0 Termination Codes

TABLE 4-15

Set Track Register Address

TABLE 4-16

Step Rate Time (SRT) Values

TABLE 4-17

Motor Off Time (MFT) Values

TABLE 4-18

Motor On Time (MNT) Values

TABLE 4-19

Verify Command Result Phase

TABLE 6-1

PC87334 UART Register Addresses (AEN e 0)

TABLE 6-2

PC87334 Register Summary for an Individual UART Channel

TABLE 6-3

PC87334 UART Reset Configuration

TABLE 6-4

PC87334 UART Divisors Baud Rates and Clock Frequencies

TABLE 6-5

PC87334 Interrupt Control Functions

TABLE 7-1

Parallel Interface Register Addresses

TABLE 7-2

Standard Parallel Port Modes Selection

TABLE 7-3

SPP Data Register Read and Write Modes

TABLE 7-4

Parallel Port Reset States

TABLE 7-5

EPP Registers

TABLE 7-6

Parallel Port Pin Out

TABLE 7-7

ECP Registers Summary

TABLE 8-1

IDE Registers and Their ISA Addresses

TABLE 10-1

Nominal tICP tDRP Values

TABLE 10-2

Minimum tWDW Values

PC87334VLJ Datasheet(PDF) 6 Page - National Semiconductor (TI)

PC87334VLJ Datasheet(HTML) 6 Page - National Semiconductor (TI)

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