S3A3 datasheet(63/139 Pages) RENESAS

63 / 139 page

R01DS0307EU0100 Rev.1.00

Page 63 of 139

Mar 7, 2017

S3A3

2. Electrical Characteristics

2.3.3

Reset Timing

Note 1.

When OFS1.LVDAS = 0.

Note 2.

When OFS1.LVDAS = 1.

Figure 2.34

Reset input timing at power-on

Figure 2.35

Reset input timing (1)

Table 2.23

Reset timing

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

RES pulse width

At power-on

tRESWP

Figure 2.34

Other than above

tRESW

μs

Figure 2.35

Wait time after RES cancellation

(at power-on)

LVD0: enable*1

tRESWT

0.7

-ms

Figure 2.34

LVD0: disable*2

0.3

Wait time after RES cancellation

(during powered-on state)

LVD0: enable*1

tRESWT2

0.5

-ms

Figure 2.35

LVD0: disable*2

0.05

Internal reset cancellation time (Watchdog

timer reset, SRAM parity error reset,

SRAM ECC error reset, Bus master MPU

error reset, Bus slave MPU error reset,

Stack pointer error reset, Software reset)

LVD0: enable*1

tRESWT3

0.6

-ms

LVD0: disable*2

0.15

VCC

RES

tRESWP

Internal reset

tRESWT

RES

Internal reset

tRESWT2

tRESW

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