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TMS320DM6431 Datasheet(PDF) 88 Page - Texas Instruments |
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TMS320DM6431 Datasheet(HTML) 88 Page - Texas Instruments |
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88 / 227 page  TMS320DM6431 Digital Media Processor SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com Table 3-20. Multiplexed Pins on DM6431 SIGNAL PINMUX DESCRIPTION ZWT ZDU NAME PINMUX GROUP CONTROLLED BY PINMUX BIT FIELDS NO. NO. PCLK/GP[54] A14 A18 EMIFA/VPSS Sub-Block 0 CCDCSEL VD/GP[53] A13 A17 EMIFA/VPSS Sub-Block 0 HVDSEL HD/GP[52] A15 A19 EMIFA/VPSS Sub-Block 0 HVDSEL EM_A[13]/GP[51] B10 A12 EMIFA/VPSS Sub-Block 0 AEM, AEAW EM_A[14]/GP[50] A10 A13 EMIFA/VPSS Sub-Block 0 AEM, AEAW EM_A[15]/GP[49] B11 C13 EMIFA/VPSS Sub-Block 0 AEM, AEAW EM_A[16]/GP[48] C11 B13 EMIFA/VPSS Sub-Block 0 AEM, AEAW EM_A[17]/GP[47] A11 B14 EMIFA/VPSS Sub-Block 0 AEM, AEAW EM_A[18]/GP[46] D11 A14 EMIFA/VPSS Sub-Block 0 AEM, AEAW CI1(CCD9)/EM_A[19]/GP[45] B12 C14 EMIFA/VPSS Sub-Block 0 AEM, AEAW, CI10SEL CI0(CCD8)/EM_A[20]/GP[44] C12 C15 EMIFA/VPSS Sub-Block 0 AEM, AEAW, CI10SEL YI7(CCD7)/GP[43] A12 A15 EMIFA/VPSS Sub-Block 0 CCDCSEL YI6(CCD6)/GP[42] B13 B15 EMIFA/VPSS Sub-Block 0 CCDCSEL YI5(CCD5)/GP[41] C13 B16 EMIFA/VPSS Sub-Block 0 CCDCSEL YI4(CCD4)/GP[40] D14 C18 EMIFA/VPSS Sub-Block 0 CCDCSEL YI3(CCD3)/GP[39] B14 A16 EMIFA/VPSS Sub-Block 0 CCDCSEL YI2(CCD2)/GP[38] C14 B17 EMIFA/VPSS Sub-Block 0 CCDCSEL YI1(CCD1)/GP[37] B15 B18 EMIFA/VPSS Sub-Block 0 CCDCSEL YI0(CCD0)/GP[36] C15 B19 EMIFA/VPSS Sub-Block 0 CCDCSEL C_WE/EM_R/W/GP[35] D13 C17 EMIFA/VPSS Sub-Block 0 AEM, CWENSEL C_FIELD/EM_A[21]/GP[34] D12 C16 EMIFA/VPSS Sub-Block 0 AEM, CFLDSEL EM_CS5/GP[33] F19 J22 EMIFA/VPSS Sub-Block 1 CS5SEL EM_CS4/GP[32] E19 H22 EMIFA/VPSS Sub-Block 1 CS4SEL GP[31] D19 G22 EMIFA/VPSS Sub-Block 1 GP[30] G19 K22 EMIFA/VPSS Sub-Block 1 GP[29] H15 K21 EMIFA/VPSS Sub-Block 1 GP[28] H16 J21 EMIFA/VPSS Sub-Block 1 GP[31:22] are standalone pins. They are not muxed with any other functions, but GP[27] H17 L19 EMIFA/VPSS Sub-Block 1 they are included in this table because GP[26]/(FASTBOOT) G17 K19 EMIFA/VPSS Sub-Block 1 they are grouped in the EMIFA/VPSS Sub-Block 1. GP[25]/(BOOTMODE3) G16 H21 EMIFA/VPSS Sub-Block 1 GP[24]/(BOOTMODE2) G15 L20 EMIFA/VPSS Sub-Block 1 GP[23]/(BOOTMODE1) F15 K20 EMIFA/VPSS Sub-Block 1 GP[22]/(BOOTMODE0) F18 J20 EMIFA/VPSS Sub-Block 1 EM_D[7]/GP[21] F17 H20 EMIFA/VPSS Sub-Block 1 AEM EM_D[6]/GP[20] F16 F21 EMIFA/VPSS Sub-Block 1 AEM EM_D[5]/GP[19] E17 F22 EMIFA/VPSS Sub-Block 1 AEM EM_D[4]/GP[18] E18 G21 EMIFA/VPSS Sub-Block 1 AEM EM_D[3]/GP[17] E16 F20 EMIFA/VPSS Sub-Block 1 AEM EM_D[2]/GP[16] D17 E22 EMIFA/VPSS Sub-Block 1 AEM EM_D[1]/GP[15] D18 G20 EMIFA/VPSS Sub-Block 1 AEM EM_D[0]/GP[14] D16 E21 EMIFA/VPSS Sub-Block 1 AEM EM_CS3/GP[13] C18 D22 EMIFA/VPSS Sub-Block 1 CS3SEL EM_CS2/GP[12] C19 C22 EMIFA/VPSS Sub-Block 1 AEM EM_A[3]/GP[11] B18 D21 EMIFA/VPSS Sub-Block 1 AEM EM_A[4]/GP[10]/(AEAW2/PLLMS2) A17 B21 EMIFA/VPSS Sub-Block 1 AEM Device Configurations 88 Submit Documentation Feedback |
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