MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33996

7

DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions of 3.1 V

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING

Output Slew Rate

SR

1.0

2.0

10

V/

µs

Output Turn ON Delay Time (Note 17)

1.0

15

50

µs

Output Turn OFF Delay Time (Note 17)

1.0

15

50

µs

Output ON Short Fault Disable Report Delay (Note 18)

100

–

450

µs

Output OFF Open Fault Delay Time (Note 18)

100

–

450

µs

Output PWM Frequency

–

–

2.0

kHz

DIGITAL INTERFACE TIMING

–

–

10

µs

Falling Edge of CS to Rising Edge of SCLK

Required Setup Time

100

–

–

ns

Falling Edge of SCLK to Rising Edge of CS

Required Setup Time

50

–

–

ns

SI to Falling Edge of SCLK

Required Setup Time

16

–

–

ns

Falling Edge of SCLK to SI

Required Hold Time

20

–

–

ns

SI, CS, SCLK Signal Rise Time (Note 20)

–

5.0

–

ns

SI, CS, SCLK Signal Fall Time (Note 20)

–

5.0

–

ns

Time from Falling Edge of CS to SO Low Impedance (Note 21)

–

–

50

ns

Time from Rising Edge of CS to SO High Impedance (Note 22)

–

–

50

ns

Time from Rising Edge of SCLK to SO Data Valid (Note 23)

–

25

80

ns

Notes

16.

Output slew rate measured across a 56

Ω resistive load.

17.

Output turn ON and OFF delay time measured from 50% rising edge of CS to 90% and 10% of initial voltage.

18.

Duration of fault before fault bit is set. Duration between access times must be greater than 450

µs to read faults.

19.

This parameter is guaranteed by design; however, it is not production tested.

20.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

21.

Time required for valid output status data to be available on SO pin.

22.

Time required for output states data to be terminated at SO pin.

23.

Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.

Freescale Semiconductor, Inc.

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