AS2845D-8 datasheet(16/20 Pages) ETC

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AS2842/3/4/5

Current Mode Controller

ASTEC Semiconductor

Resistors R1 and RF set the low frequency gain

and should be chosen to provide the highest

possible gain, without exceeding the unity gain

crossing frequency limit of fSW /4. RBIAS, in con-

junction with R1, sets the converter’s output volt-

age; but has no effect on the loop gain/phase

response.

There are a few converter design considerations

associated with the error amplifier. First, the

values of the divider network (R1 and RBIAS)

should be kept low in order to minimize errors

caused by the error amplifier’s input bias current

( –1.0

µA). An output voltage error equal to the

product of the input bias current and the equiva-

lent divider resistance, can be quite significant

with divider values greater than 5 k

Ω. Low divider

resistor values also help to improve the noise

immunity of the sensitive VFB input.

The second consideration is that the error ampli-

fier will typically source only 0.8 mA; thus, the

value of feedback resistance (RF) should be no

lower than 5 k

Ω in order to maintain the error

amplifier’s full output range. In practice, how-

ever, the feedback resistance required is usually

much greater than 5 k

Ω, hence this limitation is

normally not a problem.

Some power supply topologies may require a

more elaborate compensation network. For ex-

ample, flyback and boost converters operating

with continuous current have transfer functions

that include a right half plane (RHP) zero. These

types of systems require an additional pole

element within the compensation network.

A detailed discussion of loop compensation, how-

ever, is beyond the scope of this application note.

1.5 ISENSE current comparator/PWM latch

The current sense comparator (sometimes called

the PWM comparator) and accompanying

latch circuitry make up the pulse width modulator

(PWM). It provides pulse-by-pulse current

sensing/limiting and generates a variable duty

ratio pulse train which controls the output voltage

of the power supply. Included is a high speed

comparator followed by ECL type logic circuitry

which has very low propagation delays and switch-

ing noise. This is essential for high frequency

power supply designs. The comparator has been

designed to provide guaranteed performance

with the current sense input below ground. The

PWM latch ensures that only one pulse is al-

lowed at the output for each oscillator period.

The inverting input to the current sense compara-

tor is internally connected to the level shifted

output of the error amplifier (VE) as discussed in

the previous section. The non-inverting input is

the ISENSE input (pin 3). It monitors the switched

inductor current of the converter.

Figure 20 shows the current sense/PWM cir-

cuitry of the AS2842, and associated waveforms.

The output is set high by an internal clock pulse

and remains high until one of two conditions

occur; 1) the oscillator times out (Section 1.3 )or

2) the PWM latch is set by the current sense

comparator. During the time when the output is

high, the converter’s switching device is turned

on and current flows through resistor RS. This

produces a stepped ramp waveform at pin 3 as

shown in Figure 20. The current will continue to

ramp up until it reaches the level of VE at the

inverting input. At that point, the comparator’s

output goes high, setting the PWM latch and the

output pulse is then terminated. Thus, VE is a

variable reference for the current sense com-

parator, and it controls the peak current sensed

by RS on a cycle-by-cycle basis. VS varies in

proportion to changes in the input voltage/cur-

rent (inner control loop) while VE varies in propor-

tion to changes in the converters output voltage/

current (outer control loop). The two control loops

merge at the current sense comparator, produc-

ing a variable duty ratio pulse train that controls

the output of the converter.

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