LPC47B27X datasheet(32/196 Pages) SMSC

32 / 196 page

SMSC LPC47B27x

- 32 -

Rev. 08-10-04

DATASHEET

CONFIGURATION CONTROL REGISTER (CCR)

Address 3F7 WRITE ONLY

PC/AT and PS/2 Modes

DRATE

SEL1

DRATE

SEL0

RESET

COND.

N/A

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values.

BIT 2 - 7 RESERVED

Should be set to a logical "0"

PS/2 Model 30 Mode

NOPREC DRATE

SEL1

DRATE

SEL0

RESET

COND.

N/A

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values.

BIT 2 NO PRECOMPENSATION

This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register

mode. Unaffected by software reset.

BIT 3 - 7 RESERVED

Should be set to a logical "0"

Table 9 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the

DOR and the DSR resets.

STATUS REGISTER ENCODING

During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the

command just executed.

Table 12 - Status Register 0

BIT NO.

SYMBOL

NAME

DESCRIPTION

7,6

Interrupt Code 00 - Normal termination of command. The specified

command was properly executed and completed without

error.

01 - Abnormal termination of command.

Command

execution was started, but was not successfully

completed.

10 - Invalid command. The requested command could

not be executed.

11 - Abnormal termination caused by Polling.

Seek End

The FDC completed a Seek, Relative Seek or

Recalibrate command (used during a Sense Interrupt

Command).

Equipment

Check

The TRK0 pin failed to become a "1" after:

1. 80 step pulses in the Recalibrate command.

2. The Relative Seek command caused the FDC to

step outward beyond Track 0.

LPC47B27X Datasheet(PDF) 32 Page - SMSC Corporation

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