LPC47B27X datasheet(72/196 Pages) SMSC

72 / 196 page

SMSC LPC47B27x

- 72 -

Rev. 08-10-04

DATASHEET

Bit 6 – MIDI Transmit Busy

Bit 6 MIDI Transmit Busy indicates the send (write) state of the MIDI Data port and Command port

(Table 37).

There are no interrupts associated with MIDI transmit (write) data.

TABLE 37 - MIDI TRANSMIT BUSY STATUS BIT

STATUS PORT

DESCRIPTION

The MPU-401 interface is ready to accept a

data/command byte from the host.

The MPU-401 interface is NOT ready to

accept a data/command byte from the host.

Bits[5:0]

RESERVED (Reserved bits cannot be written and return ‘0’ when read).

Command Port

The Command port is used to transfer MPU-401 commands to the Command Controller.

The

Command port is write-only (Table 38). See Section “MPU-401 Command Controller” below.

TABLE 38 – MPU-401 COMMAND PORT

MPU-401 I/O BASE ADDRESS+1

DEFAULT

TYPE

n/a

NAME

COMMAND REGISTER

Interrupt

The MPU-401 IRQ is asserted (‘1’) when either MIDI receive data or a command acknowledge byte is

available to the host in the MIDI Data register (Figure 3). The IRQ is deasserted (‘0’) when the host

reads the MIDI Data port.

NOTE: If, following a host read, data is still available in the Receive FIFO, the IRQ will remain asserted

(‘1’).

The IRQ is enabled when the ‘Activate’ bit in the MPU-401 configuration registers logical device block is

asserted ‘1’. If the Activate bit is deasserted ‘0’, the MPU-401 IRQ cannot be asserted (see Section

“MPU-401 Configuration Registers”).

The MPU-401 IRQ is not affected by MIDI write data, transmit-related functions or Receiver Line Status

interrupts.

The factory default Sound Blaster 16 MPU-401 IRQ is 5.

MIDI RX CLOCK

MIDI RX DATA BYTE N

MIDI RX DATA BYTE N+1

MIDI_IN

DATA READY

IRQ

nREAD

NOTE: IRQ remains asserted

until read FIFO is empty

FIGURE 3 - MPU-401 INTERRUPT

NOTE

DATA READY represents the Data Ready bit B0 in the UART Line Status Register.

NOTE

nREAD represents host read operations from the MIDI Data register.

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