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PIC18F4539-E/MLSQTP Datasheet(PDF) 288 Page - Microchip Technology |
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PIC18F4539-E/MLSQTP Datasheet(HTML) 288 Page - Microchip Technology |
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288 / 322 page ![]() PIC18FXX39 DS30485A-page 286 Preliminary 2002 Microchip Technology Inc. TABLE 23-22: A/D CONVERSION REQUIREMENTS Param No. Symbol Characteristic Min Max Units Conditions 130 TAD A/D clock period PIC18FXXXX 1.6 20(4) µsTOSC based PIC18LFXXXX 2.0 6.0 µs A/D RC mode 131 TCNV Conversion time (not including acquisition time) (Note 1) 11 12 TAD 132 TACQ Acquisition time (Note 2) 5 10 — — µs µs VREF = VDD = 5.0V VREF = VDD = 2.5V 135 TSWC Switching Time from convert → sample — (Note 3) Note 1: ADRES register may be read on the following TCY cycle. 2: The time for the holding capacitor to acquire the “New” input voltage, when the new input value has not changed by more than 1 LSB from the last sampled voltage. The source impedance (RS) on the input channels is 50 Ω. See Section 18.0 for more information on acquisition time consideration. 3: On the next Q4 cycle of the device clock. 4: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. |
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