PIC18F4539-ESLASHMLSQTP datasheet(287/322 Pages) MICROCHIP

287 / 322 page

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 285

PIC18FXX39

TABLE 23-21: A/D CONVERTER CHARACTERISTICS: PIC18FXX39 (INDUSTRIAL, EXTENDED)

PIC18LFXX39 (INDUSTRIAL)

FIGURE 23-22:

A/D CONVERSION TIMING

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

A01

Resolution

—

bit

A03

EIL

Integral linearity error

—

<±1

LSb VREF = VDD = 5.0V

A04

EDL

Differential linearity error

—

<±1

LSb VREF = VDD = 5.0V

A05

Gain error

—

<±1

LSb VREF = VDD = 5.0V

A06

EOFF

Offset error

—

<±1.5

LSb VREF = VDD = 5.0V

A10

—

Monotonicity

guaranteed(2)

—VSS

≤ VAIN ≤ VREF

A20

A20A

VREF

Reference Voltage

(VREFH – VREFL)

1.8V

—

VDD < 3.0V

VDD

≥ 3.0V

A21

VREFH

Reference voltage High

AVSS

—AVDD + 0.3V

A22

VREFL

Reference voltage Low

AVSS – 0.3V

—

VREFH

A25

VAIN

Analog input voltage

AVSS – 0.3V

—

AVDD + 0.3V

VDD

≥ 2.5V (Note 3)

A30

ZAIN

Recommended impedance of

analog voltage source

——

2.5

Ω

(Note 4)

A50

IREF

VREF input current (Note 1)

—

150

µA

During VAIN acquisition

During A/D conversion cycle

Note 1: Vss

≤ VAIN ≤ VREF

2: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.

3: For VDD < 2.5V, VAIN should be limited to < .5 VDD.

4: Maximum allowed impedance for analog voltage source is 10 k

Ω. This requires higher acquisition times.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEP instruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

. . .

TCY

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