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PIC18F4539-E/MLSQTP Datasheet(PDF) 283 Page - Microchip Technology |
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PIC18F4539-E/MLSQTP Datasheet(HTML) 283 Page - Microchip Technology |
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283 / 322 page  2002 Microchip Technology Inc. Preliminary DS30485A-page 281 PIC18FXX39 TABLE 23-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. Symbol Characteristic Min Max Units Conditions 100 THIGH Clock high time 100 kHz mode 4.0 — µs PIC18FXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — µs PIC18FXXX must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 101 TLOW Clock low time 100 kHz mode 4.7 — µs PIC18FXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — µs PIC18FXXX must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 102 TR SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL fall time 100 kHz mode — 1000 ns VDD ≥ 4.2V 400 kHz mode 20 + 0.1 CB 300 ns VDD ≥ 4.2V 90 TSU:STA START condition setup time 100 kHz mode 4.7 — µs Only relevant for Repeated START condition 400 kHz mode 0.6 — µs 91 THD:STA START condition hold time 100 kHz mode 4.0 — µs After this period, the first clock pulse is generated 400 kHz mode 0.6 — µs 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 µs 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO STOP condition setup time 100 kHz mode 4.7 — µs 400 kHz mode 0.6 — µs 109 TAA Output valid from clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free before a new transmission can start 400 kHz mode 1.3 — µs D102 CB Bus capacitive loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. |
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