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PIC18F4539-E/MLSQTP Datasheet(PDF) 128 Page - Microchip Technology

Part # PIC18F4539-E/MLSQTP
Description  Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel
PDF  322 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4539-E/MLSQTP Datasheet(HTML) 128 Page - Microchip Technology

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PIC18FXX39
DS30485A-page 126
Preliminary
 2002 Microchip Technology Inc.
16.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) - Not directly
accessible
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower 6 bits of the
SSPSTAT are read only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During
transmission,
the
SSPBUF
is
not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
REGISTER 16-1:
SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
PS
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
bit 6
CKE: SPI Clock Edge Select bit
When CKP = 0:
1
= Data transmitted on rising edge of SCK
0
= Data transmitted on falling edge of SCK
When CKP = 1:
1
= Data transmitted on falling edge of SCK
0
= Data transmitted on rising edge of SCK
bit 5
D/A: Data/Address bit
Used in I2C mode only
bit 4
P: STOP bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
cleared.
bit 3
S: START bit
Used in I2C mode only
bit 2
R/W: Read/Write bit information
Used in I2C mode only
bit 1
UA: Update Address
Used in I2C mode only
bit 0
BF: Buffer Full Status bit (Receive mode only)
1
= Receive complete, SSPBUF is full
0
= Receive not complete, SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown



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