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PIC18F4539-E/MLSQTP Datasheet(PDF) 184 Page - Microchip Technology |
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PIC18F4539-E/MLSQTP Datasheet(HTML) 184 Page - Microchip Technology |
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184 / 322 page  PIC18FXX39 DS30485A-page 182 Preliminary 2002 Microchip Technology Inc. REGISTER 18-2: ADCON1 REGISTER R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’. bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold) bit 5-4 Unimplemented: Read as '0' bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx) are forced to be an analog input. ADCON1 <ADCS2> ADCON0 <ADCS1:ADCS0> Clock Conversion 0 00 FOSC/2 0 01 FOSC/8 0 10 FOSC/32 0 11 FRC (clock derived from the internal A/D RC oscillator) 1 00 FOSC/4 1 01 FOSC/16 1 10 FOSC/64 1 11 FRC (clock derived from the internal A/D RC oscillator) A = Analog input D = Digital I/O C/R = # of analog input channels / # of A/D voltage references PCFG <3:0> AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+VREF-C / R 0000 A A AA A A AA VDD VSS 8 / 0 0001 AA A A VREF+A A A AN3 VSS 7 / 1 0010 DD D A A A A A VDD VSS 5 / 0 0011 DD D A VREF+A A A AN3 VSS 4 / 1 0100 DD D D A D A A VDD VSS 3 / 0 0101 DD D D VREF+D A A AN3 VSS 2 / 1 011x DD D D D D D D — — 0 / 0 1000 AA A A VREF+VREF-A A AN3 AN2 6 / 2 1001 D D AA A A AA VDD VSS 6 / 0 1010 DD A A VREF+A A A AN3 VSS 5 / 1 1011 DD A A VREF+VREF-A A AN3 AN2 4 / 2 1100 DD D A VREF+VREF-A A AN3 AN2 3 / 2 1101 DD D D VREF+VREF-A A AN3 AN2 2 / 2 1110 DD D D D D D A VDD VSS 1 / 0 1111 DD D D VREF+VREF-D A AN3 AN2 1 / 2 |
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