S25FL032P datasheet(50/60 Pages) CYPRESS

50 / 60 page

Document Number: 002-00650 Rev. *L

Page 50 of 60

S25FL032P

Notes

1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V; 10,000 cycles; checkerboard data pattern.

2. Under worst-case conditions of 85°C; VCC = 2.7 V; 100,000 cycles.

3. Acceleration mode (9 V ACC) only in Program mode, not Erase.

4. Only applicable as a constraint for WRR instruction when SRWD is set to a ‘1’.

5. tWH + tWL must be less than or equal to 1/fC.

 Full Vcc range (2.7 – 3.6 V) & CL = 30 pF.

 Regulated Vcc range (3.0 – 3.6 V) & CL = 30 pF.

 Regulated Vcc range (3.0 – 3.6 V) & CL = 15 pF.

18.1

Capacitance

Notes

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

3. For more information on pin capacitance, please consult the IBIS models.

Figure 45. SPI Mode 0 (0,0) Input Timing

tSE

Sector Erase Time (64 KB) (1)(2)

0.5

sec

tPE

Parameter Sector Erase Time (1)(2)

(4 KB or 8 KB)

200

800

tBE

Bulk Erase Time (1)(2)

sec

tRES

Deep Power-down to Standby Mode

µs

tDP

Time to enter Deep Power-down Mode

µs

tVHH

ACC Voltage Rise and Fall time

2.2

µs

tWC

ACC at VHH and VIL or VIH to first command

µs

Table 25. AC Characteristics (Continued)

Symbol (Notes)

Parameter (Notes)

Min.

(Notes)

Typ (Notes)

Max (Notes)

Unit

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

CIN

Input Capacitance

(applies to SCK, PO7-PO0, SI, CS#)

VOUT = 0 V

9.0

12.0

COUT

Output Capacitance

(applies to PO7-PO0, SO)

VIN = 0 V

12.0

16.0

CS#

SCK

tCSH

tCSS

tCSH

tCSS

tCFT

tCRT

MSB IN

LSB IN

Hi-Z

tSU:DAT tHD:DAT

tCS

S25FL032P Datasheet(PDF) 50 Page - Cypress Semiconductor

S25FL032P Datasheet(HTML) 50 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL