S25FL032P datasheet(21/60 Pages) CYPRESS

21 / 60 page

Document Number: 002-00650 Rev. *L

Page 21 of 60

S25FL032P

9.3

Dual Output Read Mode (DOR)

The Dual Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out 2 bits at a time using 2

pins (SI/IO0 and SO/IO1) instead of 1 bit, at a maximum frequency of 80 MHz. The Dual Output Read mode effectively doubles the

data transfer rate compared to the FAST_READ instruction.

The host system must first select the device by driving CS# low. The Dual Output Read command is then written to SI, followed by a

3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. Then the memory contents, at the

address that is given, are shifted out two bits at a time through the IO0 (SI) and IO1 (SO) pins at a frequency fC on the falling edge of

SCK.

The Dual Output Read command sequence is shown in Figure 12 and Table 10 on page 18. The first address byte specified can

start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is

output. The entire memory array can therefore be read with a single Dual Output Read command. When the highest address is

reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.

It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.

The Dual Output Read command is terminated by driving CS# high at any time during data output. The device rejects any Dual

Output Read command issued while it is executing a program, erase, or Write Registers operation, and continues the operation

uninterrupted.

Figure 12. Dual Output Read Instruction Sequence

9.4

Quad Output Read Mode (QOR)

The Quad Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out 4 bits at a time using

4 pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3) instead of 1 bit, at a maximum frequency of 80 MHz. The Quad Output Read

mode effectively doubles the data transfer rate compared to the Dual Output Read instruction, and is four times the data transfer rate

of the FAST_READ instruction.

The host system must first select the device by driving CS# low. The Quad Output Read command is then written to SI, followed by

a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. Then the memory contents, at the

address that are given, are shifted out four bits at a time through IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#) pins at a

frequency fC on the falling edge of SCK.

The Quad Output Read command sequence is shown in Figure 13 and Table 10 on page 18. The first address byte specified can

start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is

output. The entire memory array can therefore be read with a single Quad Output Read command. When the highest address is

reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.

It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.

The Quad Output Read command is terminated by driving CS# high at any time during data output. The device rejects any Quad

Output Read command issued while it is executing a program, erase, or Write Registers operation, and continues the operation

uninterrupted.

The Quad bit of Configuration Register must be set (CR Bit1 = 1) to enable the Quad mode capability of the S25FL device.

CS#

SCK

SO/IO1

SI Switches from Input to Output

24 Bit

Address

Dummy Byte

Hi-Z

Byte 2

*MSB

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

22 21

32107

6543210

6420

SI/IO0

012

Instruction

Byte 1

6420

S25FL032P Datasheet(PDF) 21 Page - Cypress Semiconductor

S25FL032P Datasheet(HTML) 21 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL