S25FS128S datasheet(50/151 Pages) CYPRESS

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Document Number: 002-00368 Rev. *J

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S25FS128S

S25FS256S

7.6

Registers

Registers are small groups of memory cells used to configure how the S25FS-S family memory device operates or to report the

status of device operations. The registers are accessed by specific commands. The commands (and hexadecimal instruction codes)

used for each register are noted in each register description.

In legacy SPI memory devices the individual register bits could be a mixture of volatile, non-volatile, or One-Time Programmable

(OTP) bits within the same register. In some configuration options the type of a register bit could change e.g. from non-volatile to

volatile.

The S25FS-S family uses separate non-volatile or volatile memory cell groups (areas) to implement the different register bit types.

However, the legacy registers and commands continue to appear and behave as they always have for legacy software compatibility.

There is a non-volatile and a volatile version of each legacy register when that legacy register has volatile bits or when the command

to read the legacy register has zero read latency. When such a register is read the volatile version of the register is delivered. During

Power-On Reset (POR), hardware reset, or software reset, the non-volatile version of a register is copied to the volatile version to

provide the default state of the volatile register. When non-volatile register bits are written the non-volatile version of the register is

erased and programmed with the new bit values and the volatile version of the register is updated with the new contents of the non-

volatile version. When OTP bits are programmed the non-volatile version of the register is programmed and the appropriate bits are

updated in the volatile version of the register. When volatile register bits are written, only the volatile version of the register has the

appropriate bits updated.

The type for each bit is noted in each register description. The default state shown for each bit refers to the state after Power-On

Reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or OTP, the default state is the value of the bit

when the device is shipped from Cypress. Non-Volatile bits have the same cycling (erase and program) endurance as the main flash

array.

OTP Address Map

Region

Byte Address Range (Hex)

Contents

Initial Delivery State (Hex)

Region 0

000

Least Significant Byte of

Cypress Programmed Random

Number

Cypress Programmed Random

Number

...

00F

Most Significant Byte of Cypress

Programmed Random Number

010 to 013

Region Locking Bits

Byte 10 [bit 0] locks region 0

from programming when = 0

...

Byte 13 [bit 7] locks region

31from programming when = 0

All Bytes = FF

014 to 01F

Reserved for Future Use (RFU)

All Bytes = FF

Region 1

020 to 03F

Available for User Programming

All Bytes = FF

Region 2

040 to 05F

Available for User Programming

All Bytes = FF

...

Available for User Programming

All Bytes = FF

Region 31

3E0 to 3FF

Available for User Programming

All Bytes = FF

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