S25FS128S datasheet(21/151 Pages) CYPRESS

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S25FS128S

S25FS256S

IO floating. The memory does not use any data driven on IO during the latency cycles. The host must stop driving the IO signals on

the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so that

there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents

driver conflict between host and memory when the signal direction changes. The memory does not drive the IO signals during the

latency cycles.

The next interface state following the last latency cycle is a Quad Output Cycle.

3.3.16

Quad Output Cycle - Memory to Host Transfer

The Quad I/O Read returns data to the host four bits in each cycle. The host keeps CS# low. The memory drives data on IO0–IO3

signals during the Quad Output Cycles.

The next interface state continues to be Quad Output Cycle until the host returns CS# to high ending the command.

3.3.17

DDR Quad Input Cycle - Host to Memory Transfer

The DDR Quad I/O Read command sends address, and mode bits to the memory on all the IO signals. Four bits are transferred on

the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps CS# low.

The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.

3.3.18

DDR Latency Cycle

DDR Read commands may have one to several latency cycles during which read data is read from the main flash memory array

before transfer to the host. The number of latency cycles are determined by the Latency Code in the Configuration Register

(CR2V[3:0]). During the latency cycles, the host keeps CS# low. The host may not drive the IO signals during these cycles. So that

there is sufficient time for the host drivers to turn off before the memory begins to drive. This prevents driver conflict between host

and memory when the signal direction changes. The memory has an option to drive all the IO signals with a Data Learning Pattern

(DLP) during the last 4 latency cycles. The DLP option should not be enabled when there are fewer than five latency cycles so that

there is at least one cycle of high impedance for turn around of the IO signals before the memory begins driving the DLP. When

there are more than 4 cycles of latency the memory does not drive the IO signals until the last four cycles of latency.

The next interface state following the last latency cycle is a DDR Single, or Quad Output Cycle, depending on the instruction.

3.3.19

DDR Quad Output Cycle - Memory to Host Transfer

The DDR Quad I/O Read command returns bits to the host on all the IO signals. Four bits are transferred on the rising edge of SCK

and four bits on the falling edge in each cycle. The host keeps CS# low.

The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to high ending the command.

3.4

Configuration Register Effects on the Interface

The Configuration Register 2 volatile bits 3 to 0 (CR2V[3:0]) select the variable latency for all array read commands except Read

and Read SDFP (RSFDP). Read always has zero latency cycles. RSFDP always has 8 latency cycles. The variable latency is also

used in the OTPR, ECCRD, and RDAR commands.

The Configuration Register bit 1 (CR1V[1]) selects whether Quad Mode is enabled to switch WP# to IO2 function, RESET# to IO3

function, and thus allow Quad I/O Read and QPI Mode commands. Quad Mode must also be selected to allow DDR Quad I/O Read

commands.

3.5

Data Protection

Some basic protection against unintended changes to stored data are provided and controlled purely by the hardware design. These

are described below. Other software managed protection methods are discussed in the software section of this document.

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