S25FS128S datasheet(28/151 Pages) CYPRESS

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Document Number: 002-00368 Rev. *J

Page 28 of 151

S25FS128S

S25FS256S

5.2.1

Capacitance Characteristics

Note:

1. Parameter values are not 100% tested. For more details, please refer to the IBIS models.

5.3

Reset

5.3.1

Power-On (Cold) Reset

The device executes a Power-On Reset (POR) process until a time delay of tPU has elapsed after the moment that VCC rises above

the minimum VCC threshold. See Figure 4.3, Power-Up on page 25, and FS-S Power-Up / Power-Down Voltage and Timing

on page 24

. The device must not be selected (CS# to go high with VCC) during power-up (tPU), i.e. no commands may be sent to the

device until the end of tPU.

The IO3 / RESET# signal functions as the RESET# input when CS# is high for more than tCS time or when Quad Mode is not

enabled CR1V[1] = 0.

RESET# is ignored during POR. If RESET# is low during POR and remains low through and beyond the end of tPU, CS# must

remain high until tRH after RESET# returns high. RESET# must return high for greater than tRS before returning low to initiate a

hardware reset.

Figure 5.4

Reset Low at the End of POR

Figure 5.5

Reset High at the End of POR

Capacitance

Parameter

Test Conditions

Min

Max

Unit

CIN

Input Capacitance (applies to SCK, CS#, IO3/RESET#)

1 MHz

COUT

Output Capacitance (applies to All I/O)

1 MHz

VCC

RESET#

CS#

If RESET# is low at tPU end

CS# must be high at tPU end

tPU

tRH

VCC

RESET#

CS#

If RESET# is high at tPU end

CS# may stay high or go low at tPU end

tPU

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