S25FS128S datasheet(13/151 Pages) CYPRESS

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Document Number: 002-00368 Rev. *J

Page 13 of 151

S25FS128S

S25FS256S

Figure 2.3

Bus Master and Memory Devices on the SPI Bus — Quad Bit Data Path

Signal Protocols

3.1

SPI Clock Modes

3.1.1

Single Data Rate (SDR)

The S25FS-S family can be driven by an embedded microcontroller (bus master) in either of the two following clocking modes.

 Mode 0

with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0

 Mode 3

with CPOL = 1 and, CPHA = 1

For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the output data is

always available from the falling edge of the SCK clock signal.

The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring any data.



SCK will stay at logic low state with CPOL = 0, CPHA = 0



SCK will stay at logic high state with CPOL = 1, CPHA = 1

Figure 3.1

SPI SDR Modes Supported

Timing diagrams throughout the remainder of the document are generally shown as both Mode 0 and 3 by showing SCK as both

high and low at the fall of CS#. In some cases a timing diagram may show only Mode 0 with SCK low at the fall of CS#. In such a

case, Mode 0 timing simply means the clock is high at the fall of CS# so no SCK rising edge set up or hold time to the falling edge of

CS# is needed for Mode 0.

SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In Mode 0 the beginning of the

first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of SCK because SCK is already low

at the beginning of a command.

SPI

Bus Master

IO3 / RESET#

IO2

IO1

IO0

SCK

CS1#

FS-S

Flash

RESET# / IO3

IO2

IO0

IO1

SCK

CS1#

CPOL=0_CPHA=0_SCK

CPOL=1_CPHA=1_SCK

CS#

MSB

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