PIC16F818-ESLASHML datasheet(25/176 Pages) MICROCHIP

25 / 176 page

 2004 Microchip Technology Inc.

DS39598E-page 23

PIC16F818/819

2.3

PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low

byte comes from the PCL register, which is a readable

and writable register. The upper bits (PC<12:8>) are

not readable but are indirectly writable through the

PCLATH register. On any Reset, the upper bits of the

PC will be cleared. Figure 2-5 shows the two situations

for the loading of the PC. The upper example in the

figure shows how the PC is loaded on a write to PCL

(PCLATH<4:0>

→ PCH). The lower example in the

figure shows how the PC is loaded during a CALL or

GOTO

instruction (PCLATH<4:3>

→ PCH).

FIGURE 2-5:

LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block). Refer to the

application note AN556, “Implementing a Table Read”

(DS00556).

2.3.2

STACK

The PIC16F818/819 family has an 8-level deep x 13-bit

wide hardware stack. The stack space is not part of

either program or data space and the Stack Pointer is

not readable or writable. The PC is PUSHed onto the

stack when a CALL instruction is executed or an

interrupt causes a branch. The stack is POPed in the

event of a RETURN, RETLW or a RETFIE instruction

execution. PCLATH is not affected by a PUSH or POP

operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

2.4

Indirect Addressing: INDF and

FSR Registers

The INDF register is not a physical register. Addressing

INDF actually addresses the register whose address is

contained in the FSR register (FSR is a pointer). This is

indirect addressing.

EXAMPLE 2-1:

INDIRECT ADDRESSING

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no operation (although status bits may be affected).

A simple program to clear RAM locations, 20h-2Fh,

using indirect addressing is shown in Example 2-2.

EXAMPLE 2-2:

HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

An effective 9-bit address is obtained by concatenating

the 8-bit FSR register and the IRP bit (Status<7>) as

shown in Figure 2-6.

PCLATH<4:0>

PCLATH

Instruction with

ALU

GOTO,CALL

Opcode <10:0>

11 10

PCLATH<4:3>

PCH

PCL

PCLATH

PCH

PCL

PCL as

Destination

Note 1: There are no status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL,

RETURN,

RETLW

and RETFIE

instructions

the

vectoring

interrupt address.

• Register file 05 contains the value 10h

• Register file 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 06)

• A read of the INDF register now will return the

value of 0Ah

MOVLW

0x20

;initialize pointer

MOVWF

FSR

;to RAM

CLRF

INDF

;clear INDF register

INCF

FSR

;inc pointer

BTFSS

FSR, 4 ;all done?

GOTO

;NO, clear next

CONTINUE

;YES, continue

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