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PIC16F818-E/ML Datasheet(PDF) 100 Page - Microchip Technology |
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PIC16F818-E/ML Datasheet(HTML) 100 Page - Microchip Technology |
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100 / 176 page ![]() PIC16F818/819 DS39598E-page 98 2004 Microchip Technology Inc. 12.12 Watchdog Timer (WDT) For PIC16F818/819 devices, the WDT is driven by the INTRC oscillator. When the WDT is enabled, the INTRC (31.25 kHz) oscillator is enabled. The nominal WDT period is 16 ms and has the same accuracy as the INTRC oscillator. During normal operation, a WDT time-out generates a device Reset (Watchdog Timer Reset). If the device is in Sleep mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer wake-up). The TO bit in the Status register will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing con- figuration bit, WDTEN (see Section 12.1 “Configuration Bits”). WDT time-out period values may be found in Section 15.0 “Electrical Characteristics” under parameter #31. Values for the WDT prescaler (actually a postscaler but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. FIGURE 12-8: WATCHDOG TIMER BLOCK DIAGRAM TABLE 12-5: SUMMARY OF WATCHDOG TIMER REGISTERS Note 1: The CLRWDT and SLEEP instructions clear the WDT and the postscaler if assigned to the WDT and prevent it from timing out and generating a device Reset condition. 2: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared but the prescaler assignment is not changed. From TMR0 Clock Source (Figure 6-1) To TMR0 (Figure 6-1) Postscaler INTRC WDT Enable Bit 0 1 M U X PSA 8-to-1 MUX PS2:PS0 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register. 8 31.25 kHz Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 2007h Configuration bits(1) LVP BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of these bits. |
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