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AD6636BBCZ1 Datasheet(PDF) 1 Page - Analog Devices |
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AD6636BBCZ1 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 72 page  150 MSPS Wideband Digital Down-Converter (DDC) AD6636 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. FEATURES 4/6 independent wideband processing channels Processes 6 wideband carriers (UMTS, CDMA2000) 4 single-ended or 2 LVDS parallel input ports (16 linear bit plus 3-bit exponent) running at 150 MHz Supports 300 MSPS input using external interface logic 3 16-bit parallel output ports operating up to 200 MHz Real or complex input ports Quadrature correction and dc correction for complex inputs Supports output rate up to 34 MSPS per channel RMS/peak power monitoring of input ports Programmable attenuator control for external gain ranging 3 programmable coefficient FIR filters per channel 2 decimating half-band filters per channel 6 programmable digital AGC loops with 96 dB range Synchronous serial I/O operation (SPI®-, SPORT-compatible) Supports 8-bit or 16-bit microport modes 3.3 V I/O, 1.8 V CMOS core User-configurable built-in self-test (BIST) capability JTAG boundary scan APPLICATIONS Multicarrier, multimode digital receivers GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, TD-SCDMA Micro and pico cell systems, software radios Broadband data applications Instrumentation and test equipment Wireless local loop In-building wireless telephony FUNCTIONAL BLOCK DIAGRAM CMOS REAL PORTS A, B, C,D CMOS COMPLEX PORTS (AI, AQ) (BI, BQ) LVDS PORTS AB, CD PEAK/ RMS MEAS. I,Q CORR. SYNC [3:0] ______ RESET AGC 16-BIT MICROPORT INTERFACE SPORT/SPI INTERFACE JTAG PLL CLOCK MULTIPLIER FIR2 HB2 M = Byp, 2 CIC5 M = 1-32 NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 FIR2 HB2 M = Byp, 2 CIC5 M = 1-32 NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 FIR2 HB2 M = Byp, 2 CIC5 M = 1-32 NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 FIR2 HB2 M = Byp, 2 CIC5 M = 1-32 NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 FIR2 HB2 M = Byp, 2 CIC5 M = 1-32 NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 FIR2 HB2 M = Byp, 2 CIC5 M = 1-32 NCO FIR1 HB1 M = Byp, 2 CRCF M = 1-16 MRCF DRCF M = 1-16 LHB L = Byp, 2 PA PB PC ADC B/AQ CLKB EXPB [2:0] ADC A/AI CLKA EXPA [2:0] ADC D/CQ CLKD EXPD [2:0] ADC C/CI CLKC EXPC [2:0] M = DECIMATION L = INTERPOLATION ARE AVAILABLE ONLY IN 6-CHANNEL PART NOTE: CHANNELS RENDERED AS Figure 1. |
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