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LIS3L02DQ

6.12 A_STATUS_REG (27h)

6.13 OUTX_L (28h)

6.14 OUTX_H (29h)

When reading the register in “12 bit right justified” mode the most significant bits (7:4) are replaced with bit 3 (i.e. XD15-

XD12=XD11, XD11, XD11, XD11)

.

6.15 OUTY_L (2Ah)

ZYXOR

ZOR

YOR

XOR

ZYXDA

ZDA

YDA

XDA

ZYXOR

X, Y and Z axis Data Overrun

ZOR

Z axis Data Overrun

YOR

Y axis Data Overrun

XOR

Y axis Data Overrun

ZYXDA

X, Y and Z axis new Data Available

ZDA

Z axis new Data Available

YDA

Y axis new Data Available

XDA

X axis new Data Available

XD7XD6

XD5

XD4

XD3XD2

XD1XD0

XD7, XD0

X axis acceleration data LSb

XD15

XD14

XD13

XD12

XD11

XD10

XD9

XD8

XD15, XD8

X axis acceleration data MSb

YD7YD6

YD5

YD4

YD3YD2

YD1YD0

YD7, YD0

Y axis acceleration data LSb