HSP50214BVCZ datasheet(10/62 Pages) RENESAS

10 / 62 page

HSP50214B

FN4450 Rev 4.00

Page 10 of 62

May 1, 2007

See Figures 4 to 7 for an interpolated input example,

detailing the associated spectral results.

Interpolation Example:

The specifications for the interpolated input example are:

CLKIN = 40MHz



Input Sample Rate = 5MSPS



PROCCLK = 28MHz



Interpolate by 8, Decimate by 10



Desired 85dB dynamic range output bandwidth = 500kHz

Input Level Detector

The Input Level Detector Section measures the average

magnitude error at the PDC input for the microprocessor by

comparing the input level against a programmable

threshold and then integrating the result. It is intended to

provide a gain error for use in an AGC loop with either the

RF/IF or A/D converter stages (see Figure 8). The AGC

loop includes Input Level Detector, the microprocessor and

an external gain control amplifier (or attenuator). The input

samples are rectified and added to a threshold

programmed via the microprocessor interface, as shown in

Figure 9. The bit weighting of the data path through the

input threshold detector is shown in Figure 10. The

threshold is a signed number, so it should be set to the

inverse of the desired input level. The threshold can be set

to zero if the average input level is desired instead of the

error. The sum of the threshold and the absolute value of

the input is accumulated in a 32-bit accumulator. The

accumulator can handle up to 218 samples without

overflow. The integration time is controlled by an 18-bit

counter. The integration counter preload (ICPrel) is

programmed via the microprocessor interface through

Control Word 1. Only the upper 16-bits are programmable.

The 2 LSBs are always zero. Control Word 1, Bits 29-14

are programmed to:

where N is the desired integration period, defined as the

number of input samples to be integrated. N must be a

multiple of 4: [0, 4, 8, 12, 16 .... , 218].

ICPrel

 41



(EQ. 1)

FIGURE 3. BLOCK DIAGRAM OF THE INPUT SECTION

Without Interpolation, the CIC bypass path exceeds the HB/FIR filter

input sample rate and the CIC filter path will not yield the desired

85dB dynamic range band width of 500kHz.

FIGURE 4. STATEMENT OF THE PROBLEM

FIGURE 5. BLOCK DIAGRAM OF THE INTERPOLATION

APPROACH

IN(13:0)

INPUT_FMT

†

ENI

LEVEL

DETECT

INPUT_MODE

†

NCO

††

DELAY 3

GAINADJ(2:0)

CONTROL WORD 0

CONTROL

LOGIC

CONTROL WORD 1

CLKIN

† Controlled via microprocessor interface.

†† See NCO Section for more details.

INPUT_THRESH

†

INTG_INTEVAL

†

INTG_MODE

†

INPUT_THRESH

†

INTG_MODE

†

INTG_INTEVAL

†

INTERP

†

INPUT

FORMAT

†

BYPASS

†

INPUT LEVEL DETECTOR

†

STATUS (0)

†



LIMIT

CIC

HB/FIR FILTER

5MHz

500kHz = 85dB

BANDWIDTH

MAX. fS = 4MHz

MIN. R = 4

BYPASS

PROCCLK = 28MHz

(EXCEEDED IN

(NOT ACHIEVED

WITH CIC FILTER

BYPASS PATH)

FILTER

PATH)

CLKIN = 5MHz

CIC FILTER

8 (0 STUFF) = 40MHz

500kHz = 85dB

BANDWIDTH

R =

10

4MHz

HB/FIR FILTER

5MHz

CLKIN = 40MHz

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