CS5484 datasheet(14/67 Pages) CIRRUS

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CS5484

DS981F3

SWITCHING CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C.

• VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V.

• Logic Levels: Logic 0 = 0V, Logic 1 = VDDA.

Notes:

13.

Specified using 10% and 90% points on waveform of interest. Output loaded with 50pF.

14.

Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.

15.

The maximum SCLK is 2MHz during a byte transaction. The minimum 1µs idle time is required on the SCLK between two

consecutive bytes.

Parameter

Symbol

Min

Typ

Max

Unit

Rise Times

DO1-DO4

(Note 13)

Any Digital Output Except DO1-DO4

trise

1.0

µs

Fall Times

DO1-DO4

(Note 13)

Any Digital Output Except DO1-DO4

tfall

1.0

µs

Start-up

Oscillator Start-up Time

XTAL = 4.096 MHz (Note 14)

tost

-60-

SPI Timing

Serial Clock Frequency

(Note 15)

SCLK

MHz

Serial Clock

Pulse Width High

Pulse Width Low

200

CS Enable to SCLK Falling

Data Set-up Time prior to SCLK Rising

Data Hold Time After SCLK Rising

100

SCLK Rising Prior to CS Disable

µs

SCLK Falling to New Data Bit

150

CS Rising to SDO Hi-Z

250

UART Timing

CS Enable to RX START bit

STOP bit to CS Disable

t10

µs

CS Disable to TX IDLE Hold Time

t11

250

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