AC104X-DS00-R datasheet(27/50 Pages) BOARDCOM

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Preliminary Data Sheet

■ AC104X

12/11/01

B roa dcom Co rpo rat ion

Document

AC104X-DS00-405-R

Section 3: Register Descriptions

Page 19

* = Based on an OUI of 0010A9 (Hex)

Table 15:

Bit

Name

Description

Mode

Default

3.[15:10]

OUI

Assigned to the 19th through 24th bits of the OUI.

010101

3.[9:4]

Model Number

6-bit manufacturer’s model number.

010100

3.[3:0]

Revision Number

4-bit manufacturer’s revision number.

0010

Table 16:

Bit

Name

Description

Mode

Default

4.15

1 = Next Page enabled.

0 = Next Page disabled.

4.14

Acknowledge

This bit will be set internally after receiving 3 consecutive and

consistent FLP bursts.

4.[13:11]

Reserved

4.10

FDFC

Full-Duplex Flow Control

1= Advertise that the DTE(MAC) has implemented both the op-

tional MAC control sublayer and the pause function as specified

in clause 31 and annex 31B of 802.3u.

0= MAC does not support flow control

4.9

100BASE-T4

Technology not supported. This bit always 0

4.8

100BASE-TX

Full-Duplex

1 = 100BASE-TX full-duplex capable.

0 = Not 100BASETX full-duplex capable.

Set by

DPLX pin

4.7

100BASE-TX

1 = 100BASE-TX half-duplex capable.

0 = Not TX half-duplex capable.

4.6

10BASE-T

Full-Duplex

1 = 10BASE-T full-duplex capable.

0 = Not 10BASE-T full-duplex capable.

Set by

DPLX pin

4.5

10BASE-T

1 = 10BASE-T half-duplex capable.

0 = Not 10BASE-T half-duplex capable.

4.[4:0]

Selector Field

Protocol Selection [00001] = IEEE 802.3.

00001

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