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ADM8511 Datasheet(PDF) 41 Page - Infineon Technologies AG |
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ADM8511 Datasheet(HTML) 41 Page - Infineon Technologies AG |
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41 / 109 page  ADM8511/X Registers DescriptionSystem Registers Data Sheet 41 Rev. 2.03, 2005-11-30 RX FIFO Control BIST Control EP1C Offset Reset Value EP1 Control 1CH 00H Field Bits Type Description EPSE 7 rw EP1 Send0 Enable 0B , Disables EP1 send 1-byte 00 function 1B , Enables EP1 send 1-byte 00 when more than frame_interval’s NAK is received TIA 6:5 rw Test Interval A This value is used for internal test mode. TIB 4:0 rw Test Interval B This value is used for internal test mode. RXFC Offset Reset Value RX FIFO Control 1DH 00H Field Bits Type Description Res 7:2 ro Reserved ESE 1 rw External SRAM Enable 0B , Supports internal 24 Kbyte SRAM 1B , Supports external 32 Kbyte SRAM R32P 0 Receive 32 Packets 0B , Supports maximum 16 packets in receive FIFO 1B , Supports maximum 32 packets in receive FIFO BISTC Offset Reset Value BIST Control 1EH 01H |
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