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ISL9113AIRAZ-T Datasheet(PDF) 5 Page - Renesas Technology Corp |
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ISL9113AIRAZ-T Datasheet(HTML) 5 Page - Renesas Technology Corp |
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5 / 10 page ![]() ISL9113A FN8620 Rev 1.00 Page 5 of 10 January 4, 2017 Detailed Description Current Mode PWM Operation The control scheme of the device is based on the peak current mode control and the control loop is compensated internally. The peak current of the N-channel MOSFET switch is sensed to limit the maximum current flowing through the switch and the inductor. The typical current limit is set to 1.3A. The control circuit includes a ramp generator, slope compensator, error amplifier, and a PWM comparator (see “Block Diagram” on page 2). The ramp signal is derived from the inductor current. This ramp signal is then compared to the error amplifier output to generate the PWM gating signals for driving both N-channel and P-channel MOSFETs. The PWM operation is initialized by the clock from the internal oscillator (typical 1.8MHz). The N-channel MOSFET is turned ON at the beginning of a PWM cycle, the P-channel MOSFET remains OFF, and the current starts ramping up. When the sum of the ramp and the slope compensator output reaches the error amplifier output voltage, the PWM comparator outputs a signal to turn OFF the N-channel MOSFET. Here, both MOSFETs remain OFF during the dead-time interval. Next, the P-channel MOSFET is turned ON and remains ON until the end of this PWM cycle. During this time, the inductor current ramps down until the next clock. At this point, following a short dead time, the N-channel MOSFET is again turned ON, repeating as previously described. Skip Mode Operation The boost converter is capable of operating in two different modes. When the inductor current is sensed to cross zero for eight consecutive times, the converter enters Skip mode. In Skip mode, each pulse cycle is still synchronized by the PWM clock. The N-channel MOSFET is turned ON at the rising edge of the clock and turned OFF when the inductor peak current reaches typically 25% of the current limit. Then, the P-channel MOSFET is turned ON, and it stays ON until its current goes to zero. Subsequently, both N-channel and P-channel MOSFETs are turned OFF until the next clock cycle starts, at which time the N-channel MOSFET is turned ON again. When VOUT is 1.5% higher than the nominal output voltage, the N-channel MOSFET is immediately turned OFF, and the P-channel MOSFET is turned ON until the inductor current goes to zero. The N-channel MOSFET resumes operation when VFB falls back to its nominal value, repeating the previous operation. The converter returns to 1.8MHz PWM mode operation when VFB drops 1.5% below its nominal voltage. Given the Skip mode algorithm incorporated in the ISL9113A, the average value of the output voltage is approximately 0.75% higher than the nominal output voltage under PWM operation. This positive offset improves the load transient response when switching from Skip mode to PWM mode operation. The ripple on the output voltage is typically 1.5%*VOUT (nominal) when input voltage is sufficiently lower than output voltage, and it increases as the input voltage approaches the output voltage. Synchronous Rectifier The ISL9113A integrates one N-channel MOSFET and one P-channel MOSFET to realize a synchronous boost converter. Because the commonly used discrete Schottky rectifier is replaced with the low rDS(ON) P-channel MOSFET, the power conversion efficiency reaches a value above 90%. Since a typical step-up converter has a conduction path from the input to the output via the body diode of the P-channel MOSFET, a special circuit (see “Block Diagram” on page 2) is used to reverse the polarity of the P-channel body diode when the device is shut down. Thus, this configuration completely disconnects the load from the input during shutdown of the converter. The benefit of this feature is that the battery will not be completely depleted during shutdown of the converter. No additional components are needed to disconnect the battery from the output of the converter. Soft-Start The soft start-up duration is the time between the device being enabled and VOUT rising to within 3% of target voltage. When the device is enabled, the start-up cycle starts with a linear phase. During the linear phase, the rectifying switch is turned ON in a current limited configuration, delivering about 350mA, until the output capacitor is charged to approximately 90% of the input voltage. At this point, PWM operation begins in Boost mode. If the output voltage is below 2.3V, PWM switching is done at a fixed duty-cycle of 75% until the output voltage reaches 2.3V. When the output voltage exceeds 2.3V, the closed-loop current mode PWM loop overrides the duty cycle until the output voltage is regulated. Peak inductor current is ramped to the final value (typically 1.3A) during the soft-start period to limit inrush current from the input source. Fault monitoring begins approximately 2ms after the device is enabled. Over-Temperature Protection (OTP) The device offers over-temperature protection. A temperature sensor circuit is integrated and monitors the internal IC temperature. Once the temperature exceeds the preset threshold (typically +150°C), the IC shuts down immediately. The OTP has a typical hysteresis of +25°C. When the device temperature decreases by this, the device starts operating. Printed Circuit Board Layout Recommendations The ISL9113A is a high-frequency, switching boost converter. Accordingly, the converter has fast voltage change and high switching current that may cause EMI and stability issues if the layout is not done properly. Therefore, careful layout is critical to minimize the trace inductance and reduce the area of the power loop. Power components, such as input capacitor, inductor, and output capacitor, should be placed close to the device. Board traces that carry high switching current should be routed wide and short. A solid power ground plane is important for EMI suppression. The switching node (SW pin) of the converter and the traces connected to this pin are very noisy. Noise sensitive traces, such as the FB trace, should be kept away from SW node. The voltage divider should be placed close to the FB pin to prevent noise pickup. Figure 4 on page 6 shows the recommended PCB layout. In the 8 Ld DFN package, the heat generated in the device is mainly dissipated through the thermal pad. Maximizing the |
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