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P89LPC913FDH Datasheet(PDF) 51 Page - NXP Semiconductors |
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P89LPC913FDH Datasheet(HTML) 51 Page - NXP Semiconductors |
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51 / 63 page ![]() Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 51 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 12. Dynamic characteristics Table 14: AC characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = −40 °Cto+85 °C for industrial, unless otherwise specified.[1] Symbol Parameter Conditions Variable clock fosc =12MHz Unit Min Max Min Max fRCOSC internal RC oscillator frequency (nominal f = 7.3728 MHz) trimmed to ±1 % at Tamb =25 °C 7.189 7.557 7.189 7.557 MHz fWDOSC internal Watchdog oscillator frequency (nominal f = 400 kHz) 320 520 320 520 kHz Crystal oscillator (P89LPC912, P89LPC913) fosc oscillator frequency 0 12 - - MHz tCLCL clock cycle see Figure 29 83 - --ns fCLKP CLKLP active frequency 0 8 - - MHz Glitch filter glitch rejection, P1.5/RST pin - 50 - 50 ns signal acceptance, P1.5/RST pin 125 - 125 - ns glitch rejection, any pin except P1.5/RST - 15 - 15 ns signal acceptance, any pin except P1.5/RST 50 - 50 - ns External clock (P89LPC912, P89LPC913) tCHCX HIGH time see Figure 29 33 tCLCL − tCLCX 33 - ns tCLCX LOW time see Figure 29 33 tCLCL − tCHCX 33 - ns tCLCH rise time see Figure 29 -8 - 8 ns tCHCL fall time see Figure 29 -8 - 8 ns Shift register (UART mode 0 - P89LPC913, P89LPC914) tXLXL serial port clock cycle time see Figure 28 16 tCLCL - 1333 - ns tQVXH output data set-up to clock rising edge see Figure 28 13 tCLCL - 1083 - ns tXHQX output data hold after clock rising edge see Figure 28 -tCLCL + 20 - 103 ns tXHDX input data hold after clock rising edge see Figure 28 -0 - 0 ns tDVXH input data valid to clock rising edge see Figure 28 150 - 150 - ns |
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