ZL8802ALAFT datasheet(13/91 Pages) RENESAS

13 / 91 page

ZL8802

FN8760 Rev.3.00

Page 13 of 91

Nov 8, 2017

The ZL8802 incorporates an internal Phase-Locked Loop (PLL) to

clock the internal circuitry. The PLL can be driven by an external

clock source connected to the SYNC pin. When using the internal

oscillator, the SYNC pin can be configured as a clock source for

other Intersil digital power devices.

By default, the SYNC pin is configured as an input. The device will

automatically check for a clock signal on the SYNC pin each time

EN is asserted. The ZL8802’s oscillator will then synchronize with

the rising edge of the external clock.

The incoming clock signal must be in the range of 200kHz to

1.33MHz and must be stable when the enable pin (EN0, EN1) is

asserted. When using an external clock, the frequencies are not

limited to discrete values as when using the internal clock. The

external clock signal must not vary more than 10% from its initial

value and should have a minimum pulse width of 150ns. In the

event of a loss of the external clock signal, the output voltage

may show transient overshoot or undershoot.

If loss of synchronization occurs, the ZL8802 will automatically

switch to its internal oscillator and switch at its programmed

frequency.

When used in a multiphase (4-, 6-, and 8-phase) application, the

SYNC pin of one of the devices must be configured as an output.

The device will run from its internal oscillator and will drive the

SYNC pin so other devices can be synchronized to it. The SYNC

pin will not be checked for an incoming clock signal while in this

mode.

The switching frequency can be set to any value between 200kHz

and 1.33MHz using a PMBus command. The available

frequencies below 1.33MHz are defined by fSW = 16MHz/N,

where 12 ≤ N ≤ 80.

If a value other than fSW = 16MHz/N is entered using a PMBus

command, the internal circuitry will select the switching

frequency value using N as a whole number to achieve a value

close to the entered value. For example, if 810kHz is entered, the

device will select 800kHz (N = 20).

Input Voltage Undervoltage Lockout Setting

(UVLO)

The input Undervoltage Lockout (UVLO) prevents the ZL8802 from

operating when the input falls below a preset threshold, indicating

the input supply is out of its specified range. The input voltage

undervoltage lockout threshold can be set between 4.18V and 16V

using the pin-strap method as shown in Table 6. UVLO can also be

set or changed using the VIN_UV_FAULT_LIMIT command.

When an input undervoltage fault condition occurs, the user can

determine the desired response to the fault condition. The

following input undervoltage protection response options are

available:

• Shut down and stay off until the fault has cleared and the

device has been disabled and reenabled.

• Shut down and restart continuously after a delay.

Refer to “PMBus Command Detail” on page 27 for details on how

to select specific overvoltage fault response options using the

VIN_UV_FAULT_RESPONSE command.

When controlling the ZL8802 exclusively through the PMBus, a

high voltage setting for UVLO can be used to prevent the ZL8802

from being enabled until a lower voltage for UVLO is set using the

VIN_UV_FAULT_LIMIT command.

Configuration Setting (CFG)

The Configuration pin (CFG) sets several device configuration

settings allowing the device to be used in applications without the

need for loading configuration files. The settings are shown in

Table 7. When using the ZL8802 in a 4-phase application, the

master device address must be 1 higher than the slave address.

This must be done for the two devices to be recognized as part of a

current sharing group. See PMBus command “DDC_CONFIG

(D3h)” on page 65 for details.

13.3

267

42.2

842

14.7

286

46.4

889

16.2

320

51.1

1067

17.8

364

56.2

1143

19.6

381

61.9

1231

21.5

432

68.1

1333

TABLE 5. SWITCHING FREQUENCY SETTINGS (Continued)

RSYNC (kΩ)

FREQ (kHz)

RSYNC (kΩ)FREQ (kHz)

TABLE 6. INPUT VOLTAGE UNDERVOLTAGE LOCKOUT SETTING

RUVLO (kΩ)

UVLO (V)

RUVLO (kΩ)UVLO (V)

LOW

5.50

46.4

7.42

OPEN

4.50

51.1

8.18

HIGH

10.80

56.2

8.99

26.1

4.18

61.9

9.90

28.7

4.59

68.1

10.90

31.6

5.06

12.00

34.8

5.57

82.5

13.20

38.3

6.13

90.9

14.54

42.2

6.75

100

16.00

TABLE 7. CONFIGURATION SETTINGS

RCFG

(kΩ)

Page 0

Page 1

CIRCUIT

AVERAGE OC

LIMIT (A)

PEAK OC

LIMIT (A)

AVERAGE OC

LIMIT (A)

PEAK OC

LIMIT (A)

2 Output

37.5

2 Output

12.1

2 Output

13.3

2 Output

14.7

6065

2 Output

16.2

2 Output

17.8

37.5

2 Output

19.6

4548

2528

2 Output

21.5

2 Output

23.7

37.5

2 Output

ZL8802ALAFT Datasheet(PDF) 13 Page - Renesas Technology Corp

ZL8802ALAFT Datasheet(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datasheet Download

Link URL