P89LPC915FDH datasheet(35/72 Pages) PHILIPS

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Philips Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

Product data

Rev. 04 — 17 December 2004

35 of 72

9397 750 14397

9.9.5

Boundary limits interrupt

The A/D converters have both a high and low boundary limit register. After the four

MSBs have been converted, these four bits are compared with the four MSBs of the

boundary high and low registers. If the four MSBs of the conversion are outside the

limit an interrupt will be generated, if enabled. If the conversion result is within the

limits, the boundary limits will again be compared after all 8 bits have been converted.

An interrupt will be generated, if enabled, if the result is outside the boundary limits.

The boundary limit may be disabled by clearing the boundary limit interrupt enable.

9.9.6

DAC output to a port pin with high output impedance

The A/D converter’s DAC block can be output to a port pin. In this mode, the

AD1DAT3 register is used to hold the value fed to the DAC. After a value has been

written to AD1DAT3, the DAC output will appear on the channel 3 pin.

9.9.7

Clock divider

The A/D converter requires that its internal clock source be in the range of 500 kHz to

3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock

from 1 to 8 is provided for this purpose.

9.9.8

Power-down and Idle mode

In Idle mode the A/D converter, if enabled, will continue to function and can cause the

device to exit Idle mode when the conversion is completed if the A/D interrupt is

enabled. In Power-down mode or Total power-down mode, the A/D does not function.

If the A/D is enabled, it will consume power. Power can be reduced by disabling the

A/D.

9.10 Memory organization

The various P89LPC915/916/917 memory spaces are as follows:

• DATA

256 bytes of internal data memory space (00h:FFh) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and

status registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC915/916/917 has 2 kB of on-chip Code memory.

9.11 Interrupts

The P89LPC915/916/917 uses a four priority level interrupt structure. This allows

great ﬂexibility in controlling the handling of the many interrupt sources.

The P89LPC915 and P89LPC917 support 13 interrupt sources: external interrupts 0

and 1, timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx and Tx,

brownout detect, Watchdog/Real-Time clock, I2C, keyboard, comparators 1 and 2,

and the A/D converter.

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