P89LPC915FDH datasheet(48/72 Pages) PHILIPS

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Philips Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

Product data

Rev. 04 — 17 December 2004

48 of 72

9397 750 14397

The SPI interface has four pins: SPICLK, MOSI, MISO, and SS:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI

devices. Data ﬂows from master to slave on MOSI (Master Out Slave In) pin and

ﬂows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal

is output in the master mode and is input in the slave mode. If the SPI system is

disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are conﬁgured for port

functions.

• SS is the optional slave select pin. In a typical conﬁguration, an SPI master asserts

one of its port pins to select one SPI device as the current slave. An SPI slave

device uses its SS pin to determine whether it is selected.

Typical connections are shown in Figure 17, 18, and 19.

Fig 16. SPI block diagram (P89LPC916).

002aaa497

CPU clock

DIVIDER

BY 4, 16, 64, 128

SELECT

CLOCK LOGIC

SPI CONTROL REGISTER

READ DATA BUFFER

8-BIT SHIFT REGISTER

SPI CONTROL

SPI STATUS REGISTER

SPI clock (master)

MISO

P2.3

MOSI

P2.2

SPICLK

P2.5

P2.4

SPI

interrupt

request

internal

data

bus

MSTR

SPEN

clock

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