| Electronic Components Datasheet Search |
|
P89LPC915FDH Datasheet(PDF) 53 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
P89LPC915FDH Datasheet(HTML) 53 Page - NXP Semiconductors |
|
53 / 72 page ![]() Philips Semiconductors P89LPC915/916/917 8-bit microcontrollers with accelerated two-clock 80C51 core Product data Rev. 04 — 17 December 2004 53 of 72 9397 750 14397 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. can only be reset by a power-on reset. When the Watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 21 shows the Watchdog timer in Watchdog mode. Feeding the Watchdog requires a two-byte sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down, the Watchdog is disabled. The Watchdog timer has a time-out period that ranges from a few µs to a few seconds. Please refer to the P89LPC915/916/917 User’s Manual for more details. 9.27 Additional features 9.27.1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or Watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets. 9.27.2 Dual data pointers The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register. 9.28 Flash program memory 9.28.1 General description The P89LPC915/916/917 Flash memory provides in-circuit electrical erasure and programming. The Flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The (1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 21. Watchdog timer in Watchdog mode (WDTE = 1). PRE2 PRE1 PRE0 – – WDRUN WDTOF WDCLK WDCON (A7H) CONTROL REGISTER PRESCALER 002aaa423 SHADOW REGISTER FOR WDCON 8-BIT DOWN COUNTER WDL (C1H) Watchdog oscillator PCLK ÷32 MOV WFEED1, #0A5H MOV WFEED2, #05AH RESET see note (1) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |