CPC5750 datasheet(21/37 Pages) IXYS

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PRELIMINARY

INTEGRATED CIRCUITS DIVISION

Rev F

PRELIMINARY

CPC5750

Figure 4: PCM Time Slot 0, Short FS, No Bit Delay, 2x PCLK (PTC=PRC=0, PTB=PRB=0, CPB=1, TXZ=1)

Table 3:

PCM Interface AC Characteristics

Ambient temperature range -40°C to +85°C; VCC=VDD=3V to 3.6V

Parameter

Test Condition

Symbol

Min

Typ

Max

Units

FS Period

tFP

-125

s

FS Jitter

tFJ

100

PCLK Cycle Time

tPC

122

1955

PCLK Duty Cycle

PCLK Jitter

tPJ

±2

PCLK Rise Time

20% to 80%

tPR

PCLK Fall Time

20% to 80%

tPF

DTX Data Access Valid from PCLK Rising

tTXDA

DTX Tri-State from PCLK Rising

TXZ = 0

tTRIR

DTX Tri-State from PCLK Falling

TXZ = 1

tTRIF

FS Setup Time to PCLK Falling

tFSU

FS Hold Time from PCLK Falling

tFHD

DRX Data Setup Time to PCLK Falling

tRXSU

DRX Data Hold Time from PCLK Falling

tRXHD

LSB

MSB

HI-Z

PCLK

FRAME BIT

234567

1011121314151617

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