PRELIMINARY

Rev F

PRELIMINARY

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CPC5750

7. 4-Wire SPI (Serial Peripheral Interface)

A 4-wire, bidirectional serial interface is used for control and status monitoring when the CPC5750 is configured for

the PCM transmission mode. Typical hardware implementation of a SPI bus consists of a single master with one or

more slave devices where the role of the master is generally performed by the system controller. In PCM voice circuit

applications where a configurable CODEC is utilized such as the CPC5750, the CODEC is a slave. Data is passed

between the master and slave(s) by means of four logic signals. They are: SCLK (the serial clock); SDO (the serial

data out); SDI (the serial data in); and CS (the chip select line). Of these four logical signals, three are output by the

SPI bus master. The SPI bus master drives the CPC5750 serial data pins SCLK, SDI and CS. For the SPI bus to

function properly, the bus master’s input and output nodes must be cross connected to the SPI bus slave’s output and

input nets. This means, the master’s SDO output must be connected to the slave’s SDI input and the slave’s SDO

output must be connected to the master’s SDI input. In order to connect multiple slave devices onto the SPI bus, all

slaves must set their SDO output to high impedance (HI-Z) when not actively driving the common SDO net and each

slave must have it’s own dedicated CS connection back to the SPI bus master.

SPI bus commands issued by the system controller to the CPC5750 are eight bits in length (MSB first) and are

constructed by appending the command nibble (4 bits) with the register address nibble. The CPC5750 SPI bus

circuitry recognizes only two commands; they are READ and WRITE. For the system controller to issue a command

via the SPI bus it must drive the three SPI bus slave inputs; SCLK, CS and SDI.

Write commands are the means by which the system controller places data into one the CPC5750 control registers.

Each packet of a single register write sequence contains an 8-bit command byte appended by the 8-bit data byte to

be stored in the register listed in the command byte. The CPC5750 inputs eight bits of SDI data beginning with the

first rising edge of SCLK after CS goes active (low). When the input data byte is 0xB (1011) followed by a legitimate

four bit register address, the command is accepted and the second data byte is written into the appropriate register.

This sequence is illustrated in Figure 16.

Read commands are used by the system controller to validate the values written into the configuration registers and

to query the logical values applied to the GPIO ports configured as inputs. The read command byte sequence is the

same as described above for the write mode. The CPC5750 recognizes and accepts read commands when the input

data byte is 0xA (1010) followed by a legitimate four bit register address. With a valid read command, the CPC5750

will output the eight data bits contained in the register listed in the command byte. This data is output onto the SDO

net beginning with the MSB of the register’s contents on the first falling edge of SCLK after the rising edge of SCLK

used to clock in the LSB of the command byte. In this manner, the first control register bit will be available to the

system controller on the next rising edge of SCLK. Reliable data transfer from the CPC5750 to the system controller

requires CS to remain low while the CPC5750 is outputting data, going high only after satisfying the controller’s input

data setup and hold time requirements to ensure the last output bit is received. This sequence is illustrated in

Figure 16.

Multi-byte writes and reads are supported for single write or read commands. The register address automatically

increments after each data byte for as long as CS is active.