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CPC5750 Datasheet(PDF) 35 Page - IXYS Corporation |
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CPC5750 Datasheet(HTML) 35 Page - IXYS Corporation |
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35 / 37 page ![]() PRELIMINARY INTEGRATED CIRCUITS DIVISION Rev F PRELIMINARY 35 CPC5750 7.1 Data Compression/Expansion The differential analog signal on AIN+/- is converted and filtered as 14-bit data internally. This digital data is compressed to 8 bits as specified by the ITU G.711 standard before being transmitted in 8-bit words via the PCM bus. 8-bit data received via the PCM interface is decompressed as specified by ITU G.711 to 14-bit data before being converted to a differential analog signal, and output on the AOUT+/- signals. 7.2 Power On Reset (POR) The power-on-reset circuit will be active when power is first applied to the device. This power up active reset signal will go inactive after 20 s nominally. Additionally, a hardware reset pin (RST) is supplied to force an internal reset. The hardware reset pin is also de-bounced by the same nominal 20 s delay. |
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