PRELIMINARY

Rev F

PRELIMINARY

3

CPC5750

1. Specifications

1.1 Pinout

1.2 Pin Descriptions

Pin Name

Pin #

Pin Type

Description

Power and Ground

24

Power In

Digital Supply Voltage

23

Power In

Digital Ground

18

Power In

Analog Supply Voltage

17

Power In

Analog Ground

16

Power Out

Control Interface

RST

4

Digital Input - PU

Active low digital input with internal pull-up (PU). When asserted low, all logic is asynchronously reset.

CS

7

Digital Input

(Dual Purpose)

1) Companding selection during Power-Up or RST. Hold for 40

s after Power-Up or RST:

CS = low, Companding =

-law; CS = high, Companding = A-law. Can be modified via programming.

2) PCM Mode: SPI bus Chip Select, active low.

D0

11

Digital Input/Output

General purpose input/output pin.

D1

12

Digital Input/Output

General purpose input/output pin.

D2

13

Digital Input/Output

General purpose input/output pin.

D3

14

Digital Input/Output

General purpose input/output pin.

MUTE

15

Digital Input - PU

Active low digital input with internal pull-up. When asserted low, the analog output amplifier is disabled

SCLK

9

Digital Input

(Dual Purpose)

1) PCM Mode: SPI bus clock.

2) GCI Mode: Input, MSB address bit to select sub-frame.

SDI

10

Digital Input

(Dual Purpose)

1) Transmission Mode select during Power-Up or Reset. Hold for 40

s after Power-Up or RST:

SDI = low, Mode = IOM-2 GCI; SDI = high, Mode = PCM.

2) PCM Mode: SPI bus data input. Connects to the SPI bus master SDO output.

SDO

8

Digital Input/Output

Tri-State

(Dual Purpose)

1) PCM Mode: SPI bus data output. Connects to the SPI bus master SDI input.

2) GCI Mode: Input, address bit to select sub-frame used.

SFSEL

6

Digital Input

GCI Mode: Input LSB address bit to select sub-frame. PCM Mode: Not used.

PCM/IOM-2 Digitized Voice Interface

2

Digital Input

Receive data for PCM Interface or GCI bus.

3

Digital Output Tri-State

Transmit data for PCM Interface or GCI bus.

FS

5

Digital Input

Frame synchronization signal for GCI or PCM Interface bus.

PCLK

1

Digital Input

Master clock signal for GCI or PCM Interface bus as well as signal processing.

Analog Interface

21

Analog Input

Differential amplifier Non-inverting input.

22

Analog Input

Differential amplifier Inverting input.

19

Analog Output

Positive amplifier output, differential 600

 driver.

20

Analog Output

Negative amplifier output, differential 600

 driver.

PCLK - 1

D

D

FS - 5

SFSEL - 6

SDO - 8

SCLK - 9

SDIN - 10

D0 - 11

D1 - 12

24 - V

DD

23 - V

SS

22 - A

IN-

21 - A

IN+

20 - A

OUT-

19 - A

OUT+

18 - V

CC

17 - V

EE

16 - V

REF

15 - MUTE

14 - D3

13 - D2

RST - 4

CS - 7