RFPIC12C509AF datasheet(26/104 Pages) MICROCHIP

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rfPIC12C509AG/509AF

DS70031A-page 24

Preliminary

TABLE 5-1:

SUMMARY OF PORT REGISTERS

5.4

I/O Programming Considerations

5.4.1

BI-DIRECTIONAL I/O PORTS

Some instructions operate internally as read followed

by write operations. The BCF and BSF instructions, for

example, read the entire port into the CPU, execute the

bit operation and re-write the result. Caution must be

used when these instructions are applied to a port

where one or more pins are used as input/outputs. For

example, a BSF operationonbit5of GPIO will causeall

eight bits of GPIO to be read into the CPU, bit5 to be

set and the GPIO value to be written to the output

latches. If another bit of GPIO is used as a bi-direc-

tional I/O pin (say bit0) and it is defined as an input at

this time, the input signal present on the pin itself would

be read into the CPU and rewritten to the data latch of

this particular pin, overwriting the previous content. As

long as the pin stays in the input mode, no problem

occurs. However, if bit0 is switched into output mode

later on, the content of the data latch may now be

unknown.

Example 5-1 shows the effect of two sequential read-

modify-write instructions (e.g., BCF, BSF, etc.) on an I/

Oport.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-and”).

The resulting high output currents may damage the

chip.

EXAMPLE 5-1:

Read-Modify-Write

Instructions on an

I/O Port

;Initial GPIO Settings

; GPIO<5:3> Inputs

; GPIO<2:0> Outputs

;

GPIO latch

GPIO pins

;

----------

BCF

GPIO, 5

;--01 -ppp

--11 pppp

BCF

GPIO, 4

;--10 -ppp

--11 pppp

MOVLW 007h

;

TRIS

GPIO

;--10 -ppp

--11 pppp

;

;Note that the user may have expected the pin

;values to be --00 pppp. The 2nd BCF caused

;GP5 to be latched as the pin value (High).

5.4.2

SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle (Figure 5-

2). Therefore, care must be exercised if a write followed

by a read operation is carried out on the same I/O port.

The sequence of instructions should allow the pin volt-

age to stabilize (load dependent) before the next

instruction, whichcauses that filetobereadinto the

CPU, is executed. Otherwise, the previous state of that

pin may be read into the CPU rather than the new state.

When in doubt, it is better to separate these instruc-

tions with a NOP or another instruction not accessing

this I/O port.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-on

Reset

Value on

All Other

RESETS

N/A

TRIS

—

--11 1111

N/A

OPTION

GPWU

GPPU

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

03H

STATUS

GPWUF

—

PAO

0001 1xxx

q00q quuu

(1)

06h

GPIO

—

GP5

GP4

GP3

GP2

GP1

GP0

--xx xxxx

--uu uuuu

Legend:

Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u =

unchanged, q = see tables in Section 8.7 for possible values.

Note 1: If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0.

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