DSP56857 datasheet(651/662 Pages) FREESCALE

651 / 662 page

INDEX

Index, Rev. 4

Freescale Semiconductor

Index -i

Symbols

(CAP) Timer Channel Capture Register 13-17

(CGMDB) CGM Divide-By Register 6-15

(CGMTOD) Time of Day CGM Register 6-16

(CMP1) Timer Channel Compare Register 1 13-16

(CMP2) Timer Channel Compare Register 2 13-16

(CNTR) Timer Channel Counter Register 13-18

(CTL) Timer Control Registers 13-11

(CVR) Command Vector Register Host Side HI8 16-23

(DMACNT) Transfer Count 9-11

(DMACQS) Circular Queue Size 9-10

(DMADAL) Destination Address Low 9-11

(DMASAL) Source Address Low 9-12

(DMATC) Transfer Control 9-8

(FIM0, FIM1) Fast Interrupt Match Registers 8-26

(FIVAH1) Fast Interrupt 1 Vector Address High

(FIVAL0, FIVAH0, FIVAL1, FIVAH1) Fast Interrupt Match

Registers 8-27

(FIVAL1) Fast Interrupt 1 Vector Address Low Register 8-28

(HCR) DSC Side Control Register HI8 16-10

(HOLD) Timer Channel Hold Register 13-17

(HRX) DSC Side Receive Data Register HI8 16-15

(HSR) DSC Side Status Register HI8 16-13

(HTX) DSC Side Transmit Data Register HI8 16-15

(ICR) Host Side Interface Control Register HI8 16-18

(ICTL) Interrupt Control Register 8-30

(IPR1) Interrupt Priority Register 1 8-9

(IPR2) Interrupt Priority Register 2 8-10

(IPR3) Interrupt Priority Register 3 8-12

(IPR4) Interrupt Priority Register 4 8-14

(IPR5) Interrupt Priority Register 5 8-16

(IPR6) Interrupt Priority Register 6 8-19

(IPR7) Interrupt Priority Register 7 8-21

(IRQ0, IRQ1, IRQ3, IRQ4) Pending Registers IRQ 8-29

(ISR) Interface Status Register Host Side HI8 16-24

(IVR) Interrupt Vector Register Host Side HI8 16-26

(LOAD) Timer Channel Load Register 13-17

(MISO) Master In/Slave Out 11-5

(MOSI) Master Out/Slave In 11-5

(MPA_DDR) Port A Direction Register GPIO 15-14

(MPA_DR) Port A Data Register GPIO 15-18

(MPA_PER) Port A Peripheral Enable Register 15-10

(MPA_PUE) Port A Pull-Up Enable Register GPIO 15-21

(MPB_DDR) Port B Direction Register 15-14

(MPB_DR) Port B Data Register GPIO 15-18

(MPB_PER) Port B Peripheral Enable Register GPIO 15-10

(MPB_PUE) Port B Pull-Up Enable Register GPIO 15-22

(MPC_DDR) Port C Direction Register GPIO 15-15

(MPC_DR) Port C Data Register GPIO 15-18

(MPC_PER) Port C Peripheral Enable Register

GPIO 15-11

(MPC_PUE) Port C Pull-Up Enable Register GPIO 15-22

(MPD_DDR) Port D Direction Register GPIO 15-15

(MPD_DR) Port D Data Register GPIO 15-19

(MPD_PER) Port D Peripheral Enable Register

GPIO 15-11

(MPD_PUE) Port D Pull-Up Enable Register GPIO 15-23

(MPE_DDR) Port E Direction Register GPIO 15-16

(MPE_DR) Port E Data Register GPIO 15-19

(MPE_PER) Port E Peripheral Enable Register

GPIO 15-12

(MPE_PUE) Port E Pull-Up Enable Register GPIO 15-23

(MPF_DDR) Port F Direction Register GPIO 15-16

(MPF_DR) Port F Data Register GPIO 15-20

(MPF_PER) Port F Peripheral Enables Register

GPIO 15-12

(MPF_PUE) Port F Pull-Up Enable Register GPIO 15-24

(MPG_DDR) Port G Direction Register GPIO 15-17

(MPG_DR) Port G Data Register GPIO 15-20

(MPG_PER) Port G Peripheral Enables Register

GPIO 15-13

(MPG_PUE) Port G Pull-Up Enable Register GPIO 15-24

(MPH_DDR) Port H Direction Register GPIO 15-17

(MPH_DR) Port H Data Register GPIO 15-21

(MPH_PER) Port H Peripheral Enables Register

GPIO 15-13

(MPH_PUE) Port H Pull-Up Enable Register GPIO 15-25

(RLS) Receive Last Slot ESSI 12-64

(RSMA, RSMB) Receive Slot Mask Registers 12-58

(RX) Receive Data ESSI 12-64

(RXD) Receive Data 10-4

(RXFIFO) Receive FIFO Register 12-29

(RXH, RXL) Receive Byte Registers Host Side HI8 16-27

(RXSR) Receive Shift Register 12-30

(SCD1) SIM Software Control Data 1 4-13

(SCD2) SIM Software Control Data 2 4-13

(SCICR) Control Register 10-23

(SCICR2) Control Register 2 10-27

(SCIDR) Data Register 10-31

(SCISR) Status Register 10-28

(SCLK) Serial Clock 11-5

(SCR) Control Register SIM 4-9

(SCR) Timer Channel Status and Control Registers 13-14

(SCR2) Control Register 12-37

(SCR3) Control Register 12-43

(SCR4) Control Register 4 12-47

(SFCSR) FIFO Control/Status Register 12-54

(SPDRR) Data Receive Register 11-28

(SPDSCR) Data Size and Control Register 11-26

(SPDTR) Data Transmit Register 11-28

DSP56857 Datasheet(PDF) 651 Page - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 651 Page - Freescale Semiconductor, Inc

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