DSP56857 datasheet(654/662 Pages) FREESCALE

654 / 662 page

Index, Rev. 4

Index - iv

Freescale Semiconductor

Network Mode 12-14

Network Mode with Mask Registers

Implemented 12-19

Normal Mode 12-10

Receive Data (RX) 12-64

Receive Data With Exception 12-63

Receive FIFO Register (RXFIFO) 12-29

Receive Last Slot (RLS) 12-64

Receive Register (SRX) 12-29

Receive Shift Register (RXSR) 12-30

Receive Slot Mask Registers (RSMA, RSMB) 12-58

Resets 12-62

Signal Descriptions 12-4

Signal Properties 12-4

Status Register (SSR) 12-31

Time Slot Register (STSR) 12-53

Transmit Data (TX) 12-64

Transmit Data With Exception 12-64

Transmit FIFO Registers (TXFIFO0, TXFIFO1,

TXFIFO2) 12-27

Transmit Last Slot (TLS) 12-65

Transmit Registers (STX0, STX1, STX2) 12-26

Transmit Shift Registers (TXSR0, TXSR1,

TXSR2) 12-28

Transmit Slot Mask Registers (TSMA, TSMB) 12-57

ESSI (Enhanced Synchronour Serial Interface) 1-30

ESSI Enable (ESSIEN) 12-42

EX A-6

EXTBOOT A-6

External Frame Sync Setup ISSI 12-65

External I/O Signals SPI 11-6

External Memory Interface (EMI) 1-28

External Signals Descriptions ESSI 12-4

EXTR A-6

FAULT A-6

FE A-6

Feature Matrix 1-12

FH A-6

FIEx A-6

FIR A-6

Fixed Frequency PWM Mode TMR 13-8

Flash memory A-6

FLOCI A-6

FLOLI A-6

FMODEx A-6

FPINx A-7

FTACKx A-7

Fucntional Description ESSI 12-10

Functional Description GPIO 15-4

Functional Description SCI 10-6

Functional Description TMR 13-4

Functionl Description ITCN 8-7

Gated Count Mode TMR 13-6

General Information TOD 14-7

General Purpose I/O Port (GPIO) 1-29

GPIO A-7

(General Purpose Input/Output) 1-29

Block Diagram 15-3

Configuration 15-5

Data Register Access 15-25

Features 15-3

Functional Description 15-4

GPIO Mode 15-4

Interrupts 15-26

Modes of Operation 15-4

Normal Mode 15-4

Port A Data Register (MPA_DR) 15-18

Port A Direction Register (MPA_DDR) 15-14

Port A Peripheral Enable Register (MPA_PER) 15-10

Port A Pull-Up Enable Register (MPA_PUE) 15-21

Port B Data Register (MPB_DR) 15-18

Port B Direction Register (MPB_DDR) 15-14

Port B Peripheral Enable Register (MPB_PER) 15-10

Port B Pull-Up Enable Register (MPB_PUE) 15-22

Port C Data Register (MPC_DR) 15-18

Port C Direction Register (MPC_DDR) 15-15

Port C Peripheral Enable Register (MPC_PER) 15-11

Port C Pull-Up Enable Register (MPC_PUE) 15-22

Port D Data Register (MPD_DR) 15-19

Port D Direction Register (MPD_DDR) 15-15

Port D Peripheral Enable Register (MPD_PER) 15-11

Port D Pull-Up Enable Register (MPD_PUE) 15-23

Port E Data Register (MPE_DR) 15-19

Port E Direction Register (MPE_DDR) 15-16

Port E Peripheral Enable Register (MPE_PER) 15-12

Port E Pull-Up Enable Register (MPE_PUE) 15-23

Port F Data Register (MPF_DR) 15-20

Port F Direction Register (MPF_DDR) 15-16

Port F Peripheral Enables Register (MPF_PER) 15-12

Port F Pull-Up Enable Register (MPF_PUE) 15-24

Port G Data Register (MPG_DR) 15-20

Port G Direction Register (MPG_DDR) 15-17

Port G Peripheral Enables Register (MPG_PER) 15-13

Port G Pull-Up Enable Register (MPG_PUE) 15-24

Port H Data Register (MPH_DR) 15-21

Port H Direction Register (MPH_DDR) 15-17

Port H Peripheral Enables Register (MPH_PER) 15-13

DSP56857 Datasheet(PDF) 654 Page - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 654 Page - Freescale Semiconductor, Inc

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