DSP56857 datasheet(655/662 Pages) FREESCALE

655 / 662 page

Index, Rev. 4

Freescale Semiconductors

Index - v

Port H Pull-Up Enable Register (MPH_PUE) 15-25

, 15-9

Resets 15-26

GPR A-7

Harvard architecture A-7

HBO A-7

HI8

Block Diagram 16-7

DSC Core Interrupts 16-16

DSC Side Features 16-3

DSC Side HI8 Control Register (HCR) 16-10

DSC Side HI8 Receive Data Register (HRX) 16-15

DSC Side HI8 Register Descriptions 16-8

DSC Side HI8 Status Register (HSR) 16-13

DSC Side HI8 Transmit Data Register (HTX) 16-15

DSC Side Registers After Reset 16-15

Features 16-3

Host Port 16-5

Host Port Use Considerations 16-35

Host Processor Data Transfer 16-30

Host Side Command Vector Register (CVR) 16-23

Host Side DMA Mode Operation 16-32

Host Side Features 16-4

Host Side HI8 Register Descriptions 16-9

Host Side Interface Control Register (ICR) 16-18

Host Side Interface Status Register (ISR) 16-24

Host Side Interrupt Vector Register (IVR) 16-26

Host Side Polling 16-30

Host Side Receive Byte Registers (RXH, RXL) 16-27

Host Side Registers 16-17

Host Side Registers After Reset 16-29

Host Side Transmit Byte Registers (TXH, TXL) 16-28

Servicing Interrupts Host Side 16-31

Servicing the Host Interface 16-24

Signal Desctiptions 16-5

HLMTI A-7

HLMTIE A-7

HOLD A-7

HOME A-7

Host Control Interrupt Vector ITCN 8-35

Host Port HI8 16-5

Host Side Registers HI8 16-17

Host Side Servicing Interrupts HI8 16-31

I/O A-8

IA A-8

IC A-8

IE A-8

IEE A-8

IEF A-8

IEFIE A-8

IENR A-8

IES A-8

IFREN A-8

IMR A-8

INDEP A-8

INDEX A-8

INPUT A-8

Interface Signals SIM 4-6

Interrupt Handshake Timing ITCN 8-36

Interrupt Operation Description ESSI 12-63

Interrupt Vectors 3-19

INV A-8

IP A-8

IPBus A-8

IPBus Bridge 1-22

IPE A-8

IPOL A-8

IPOLR A-8

IPR A-8

IPS A-9

IRQ A-9

IS A-9

ISSI

External Frame Sync Setup 12-65

Maximum External Clock Rate 12-65

ITCN A-9

After Reset 8-36

Block Diagram 8-7

Fast Interrupt 1 Vector Address High Register

(FIVAH1) 8-28

Fast Interrupt 1 Vector Address Low Register

(FIVAL1) 8-28

Fast Interrupt Match Registers (FIM0, FIM1) 8-26

Fast Interrupt Vector Address Registers (FIVAL0,

FIVAH0, FIVAL1, FIVAH1) 8-27

Features 8-4

Functional Description 8-7

Host Control Interrupt Vector 8-35

Interrupt Control Register (ICTL) 8-30

Interrupt Handshake Timing 8-36

Interrupt Nesting 8-37

DSP56857 Datasheet(PDF) 655 Page - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 655 Page - Freescale Semiconductor, Inc

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