DSP56857 datasheet(656/662 Pages) FREESCALE

656 / 662 page

Index, Rev. 4

Index - vi

Freescale Semiconductor

Interrupt Priortity Register 1 (IPR1) 8-9

Interrupt Priortity Register 2 (IPR2) 8-10

Interrupt Priortity Register 3 (IPR3) 8-12

Interrupt Priortity Register 4 (IPR4) 8-14

Interrupt Priortity Register 5 (IPR5) 8-16

Interrupt Priortity Register 6 (IPR6) 8-19

Interrupt Priortity Register 7 (IPR7) 8-21

Interrupt Vector Map 8-32

Interrupts 8-36

IRQ Pending Registers (IRQ0, IRQ1, IRQ3,

IRQ4) 8-29

Module Memory Map 8-5

Reset Handshake Timing 8-36

Resets 8-36

Signal Description 8-4

Vector Base Address Register (VBA) 8-25

Wait and Stop Mode Operations 8-35

JTAG A-9

TAP Block Diagram 17-5

TAP Controller 17-19

TCK pin 17-5

TDI pin 17-5

TDO pin 17-5

Test Clock Input pin (TCK) 17-5

Test Data Input pin (TDI) 17-5

Test Data Output pin (TDO) 17-5

Test Mode Select Input pin (TMS) 17-5

Test Reset/Debug Event pin (TRST/DE) 17-5

TMS pin 17-5

TRST/DE pin 17-5

JTAG/EOnCE port 1-33

JTAGBR A-9

JTAGIR A-9

LCD A-9

LCK A-9

LDOK A-9

LIR A-9

LLMTI A-9

LLMTIE A-9

LOAD A-9

LOCI A-9

LOCIE A-9

LOLI A-9

LOOP A-9

Loop Operation SCI 10-20

LPOS A-9

LPOSH A-9

LSB A-9

LSH_ID A-9

LVD A-9

LVIE A-9

LVIS A-9

MA A-9

MAC A-10

MAS A-10

Maximum External Clock Rate ISSI 12-65

MB A-10

MCU A-10

Memory Map CGM 6-13

Memory Map ITCN 8-5

Memory Map SPI 11-21

Memory Maps 5685x 3-6

Method of Operation POR 7-4

MHz A-10

MIPS A-10

MISO A-10

Mode Fault Error SPI 11-19

Modes of Operation GPIO 15-4

MODF A-10

MODFEN A-10

MOSI A-10

MPIO A-10

MSB A-10

MSCAN A-10

MSH_ID A-10

MSTR A-10

MUX A-10

Nesting Interrupt ITCN 8-37

Network Mode with Implemented Mask Registers

ESSI 12-19

NL A-10

NOR A-10

Normal Mode GPIO 15-4

NVSTR A-10

OBAR A-10

OBCTL A-10

OBMSK A-10

OCCS A-10

OCMDR A-10

OCNTR A-10

OCR A-10

DSP56857 Datasheet(PDF) 656 Page - Freescale Semiconductor, Inc

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