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DSP56857 Datasheet(PDF) 658 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 658 Page - Freescale Semiconductor, Inc |
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658 / 662 page ![]() Index, Rev. 4 Index - viii Freescale Semiconductor ROM A-13 RPD A-13 RSRC A-13 RWU A-13 S SA A-13 SBK A-13 SBO A-13 SBR A-13 SCI 1-29 , A-13 Baud Rate Generation 10-7 Baud Rate Tolerance 10-17 Control Register (SCICR) 10-23 Control Register 2 (SCICR2) 10-27 Data Frame Format 10-6 Data Register (SCIDR) 10-31 DMA Operation 10-21 Features 10-3 Functional Diagram 10-6 Interrupt Sources 10-32 Loop Operation 10-20 Low Power Options 10-22 Receive Data (RXD) 10-4 Receiver Block Diagram 10-11 Receiver DMA Operation 10-21 Receiver Wake Up with DMA 10-21 Recovery From Wait Mode 10-22 Recovery from Wait Mode 10-32 Register Descriptions 10-23 Run Mode 10-22 SCI0 and SCI1 Memory Maps 10-5 Single Wire Operation 10-20 Status Register (SCISR) 10-28 Stop Mode 10-22 Transmit Data (TXD) 10-4 Transmit DMA Operation 10-21 Transmitter Block Diagram 10-8 Wait Mode 10-22 SCI (Serial Communications Interface) 1-29 SCIBR A-13 SCICR A-13 SCIDR A-13 SCISR A-13 SCLK A-13 SCR A-13 SD A-13 SDK A-13 Serial Communications Interface (SCI) 1-29 SEXT A-13 Signal Description DMA 9-3 Signal Description HI8 16-5 Signal Description ITCN 8-4 Signal Description SIM 4-6 Signal Descriptions ESSI 12-4 Signal Properties ESSI 12-4 Signed Count Mode TMR 13-7 SIM A-13 Block Diagram 4-4 Clock Generation Concepts 4-14 Clock Signals 4-15 Control Register (SCR) 4-9 Features 4-3 Generated Clocks 4-15 Interface Signals 4-6 Power Mode Controls 4-16 Register Descriptions 4-9 Register Map 4-8 Resets 4-17 Signal Description 4-6 Software Control Data 1 (SCD1) 4-13 Software Control Data 2 (SCD2) 4-13 Single Wire Operation SCI 10-20 SMODE A-13 Source Address High (DMASAH) 9-12 SP A-14 SPDRR A-13 SPDSR A-13 SPDTR A-13 SPI A-14 Clock Phase and Polarity Controls 11-11 Data Receive Register (SPDRR) 11-27 Data Shift Odering 11-11 Data Size and Control Register (SPDSCR) 11-26 Data Transmission Length 11-11 Data Transmit Register (SPDTR) 11-28 Error Conditions 11-17 External I/O Signals 11-6 Features 11-3 Interrupts 11-29 Master In/Slave Out (MISO) 11-5 Master Out/Slave In (MOSI) 11-5 Memory Map 11-18 Mode Fault Error 11-19 Overflow Error 11-17 Pin Descriptions 11-5 Register Descriptions 11-22 Resets 11-28 Serial Clock (SCLK) 11-5 Slave Mode 11-8 Slave Select (SS) 11-5 Status and Control Register (SPSCR) 11-22 Transmission Data 11-15 |
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