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DSP56857 Datasheet(PDF) 653 Page - Freescale Semiconductor, Inc

Part # DSP56857
Description  Digitial Signal Controller
PDF  662 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 653 Page - Freescale Semiconductor, Inc

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Index, Rev. 4
Freescale Semiconductors
Index - iii
Controller Block Diagram 9-7
COP A-4
COP/RTI A-4
COP/Watchdog Timer Module 1-32
COPCTL A-4
COPDIS A-4
COPR A-4
COPSRV A-5
COPTO A-5
Core Interrupts HI8 16-16
Count Mode TMR 13-6
Counting Mode Definitions 14-7
Counting Modes of Definitions TMR 13-5
CPHA A-5
CPOL A-5
CPU A-5
CRC A-5
CSEN A-5
CTRL A-5
CTRL PD A-5
CWEN A-5
CWP A-5
D
DAC A-5
DAT A-5
Data Frame Format SCI 10-6
DATA PD A-5
Data Register Access GPIO 15-25
Data Shift Ordering SPI 11-11
Data SRAM 1-25
Data Transfer HI8 Host Processor 16-30
Data Transmission Length SPI 11-11
DDA A-5
DDR A-5
DEC A-5
DEE A-5
DFIU A-5
DFLASH A-5
DIRQ A-5
DMA
Circular Queue Size (DMACQS) 9-10
Controller Block Diagram 9-7
Features 9-3
Memory-to-Memory DMA Operation 9-14
Mode Operation Host Side HI8 16-32
Peripheral-to-Memory Circular Queue DMA
Operation 9-15
Peripheral-to-Memory DMA Operation 9-13
Programming Examples 9-13
Register Descriptions 9-8
Register Maps 9-5
Signal Description 9-3
Source Address High (DMASAH) 9-12
Source Address Low (DAMSAL) 9-12
Transfer Control (DMATC) 9-8
Transfer Count (DMACNT) 9-11
DPE A-6
DR A-6
DRV A-6
DSO A-6
DSP A-6
DSP56853 Peripheral Blocks 1-26
DSP56854 Peripheral Blocks 1-26
DSP56855 Peripheral Blocks 1-27
DSP56857 Peripheral Blocks 1-27
DSP56858 Peripheral Blocks 1-28
DSP5685x Memory Maps 3-6
E
EDG A-6
Edge Count Mode TMR 13-6
EE A-6
EEOF A-6
EM A-6
EMI (External Memory Interface) 1-28
EN A-6
ENCR A-6
Enhanced On-Chip Emulation (EOnCE) 1-33
Enhanced On-Chip Emulation (EOnCE) Module 1-21
Enhanced Synchronour Serial Interface (ESSI) 1-30
EOnCE Enhanced On-Chip Emulation Module) 1-21
EOSI A-6
EOSIE A-6
ERASE A-6
ERRIE A-6
Error Conditions SPI 11-17
ESSI
Block Diagram 12-8
Clock and Frame Sync Generation 12-60
Clock Operation Description 12-60
Clocks 12-59
Configurations 12-23
Control Register 2 (SCR2) 12-37
Control Register 3 (SCR3) 12-43
Control Register 4 (SCR4) 12-47
External Signals Descriptions 12-4
Features 12-3
FIFO Control/Status Register (SFCSR) 12-54
Fucntional Description 12-10
Interrupt Operation Description 12-63
Interrupts 12-63



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