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NT5CB256M8FN-DI Datasheet(PDF) 22 Page - Nanya Technology Corporation. |
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NT5CB256M8FN-DI Datasheet(HTML) 22 Page - Nanya Technology Corporation. |
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22 / 163 page  DDR3(L) 2Gb SDRAM NT5CB(C)256M8FN / NT5CB(C)128M16FP Version 1.7 22 Nanya Technology Cooperation © 04/2015 All Rights Reserved. Additive Latency (AL) Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidth in DDR3(L) SDRAM. In this operation, the DDR3(L) SDRAM allows a read or write command (either with or without auto-precharge) to be issued immediately after the active command. The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A summary of the AL register options are shown as the following table. Additive Latency (AL) Settings A4 A3 AL 0 0 0, (AL Disable) 0 1 CL-1 1 0 CL-2 1 1 Reserved |
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