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NT5CB256M8FN-DI Datasheet(PDF) 49 Page - Nanya Technology Corporation. |
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NT5CB256M8FN-DI Datasheet(HTML) 49 Page - Nanya Technology Corporation. |
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49 / 163 page  DDR3(L) 2Gb SDRAM NT5CB(C)256M8FN / NT5CB(C)128M16FP Version 1.7 49 Nanya Technology Cooperation © 04/2015 All Rights Reserved. READ Operation Read Burst Operation During a READ or WRITE command DDR3(L) will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled). A12=0, BC4 (BC4 = burst chop, tCCD=4) A12=1, BL8 A12 will be used only for burst length control, not a column address. Read Burst Operation RL=5 (AL=0, CL=5, BL=8) READ Burst Operation RL = 9 (AL=4, CL=5, BL=8) CK CK T0 T1 T3 T5 T6 T7 T9 CL=5 DQS, DQS T2 T4 T8 T10 READ NOP CMD NOP NOP NOP NOP NOP NOP NOP NOP NOP Bank Col n Address Dout n Dout n +1 Dout n +2 Dout n +3 Dout n +4 Dout n +5 Dout n +6 Dout n +7 DQ RL = AL + CL tRPRE tRPST CK CK T0 T1 T3 T5 T6 T7 T9 CL=5 DQS, DQS T2 T4 T8 T10 READ NOP CMD NOP NOP NOP NOP NOP NOP NOP NOP NOP Bank Col n Address Dout n Dout n +1 Dout n +2 Dout n +3 DQ RL = AL + CL tRPRE AL = 4 |
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