NT5CB256M8FN-DI datasheet(35/163 Pages) NANYA

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DDR3(L) 2Gb SDRAM

NT5CB(C)256M8FN / NT5CB(C)128M16FP

Version 1.7

Nanya Technology Cooperation ©

04/2015

DLL on/off switching procedure

DDR3(L) DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit

set back to “0”.

DLL “on” to DLL “off” Procedure

To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh outlined in the following

procedure:

1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT, must

be in high impedance state before MRS to MR1 to disable the DLL).

2. Set MR1 Bit A0 to “1” to disable the DLL.

3. Wait tMOD.

4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.

5. Change frequency, in guidance with “Input Clock Frequency Change” section.

6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.

7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from any

MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh

mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any MRS

command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was entered,

ODT signal can be registered LOW or HIGH.

8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be

necessary. A ZQCL command may also be issued after tXS).

9. Wait for tMOD, and then DRAM is ready for next command.

NT5CB256M8FN-DI Datasheet(PDF) 35 Page - Nanya Technology Corporation.